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* OneNAND: Additional sync with 2.6.27Stefan Roese2009-01-23-1/+72
| | | | | | | | | | | | - Add subpage write support - Add onenand_oob_64/32 ecclayout This has been missing and without it UBI has some incompatibilies issues with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is placed differently (2048 instead of 512) without this fix. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Add markbad functionKyungmin Park2009-01-23-0/+33
| | | | | | | Add missing markbad function If not, it's hang when it entered the mtd->mark_bad(). Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* OneNAND: Bad block aware read/write command supportStefan Roese2009-01-23-110/+420
| | | | | | | | | Update OneNAND command to support bad block awareness. Also change the OneNAND command style to better match the NAND version. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
* OneNAND: Save version_id in onenand_chip structStefan Roese2009-01-23-0/+1
| | | | | | | | The version (ver_id) was not stored in the onenand_chip structure and because of this the continuous locking scheme could be enabled on some chips. Signed-off-by: Stefan Roese <sr@denx.de>
* OneNAND: Fix compiler warningsStefan Roese2009-01-23-0/+26
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* mpc83xx: enable eLBC NAND support for MPC8315ERDB boardDave Liu2009-01-23-5/+7
| | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
* Sync with 2.6.27Kyungmin Park2009-01-23-179/+406
| | | | | | Sync with OneNAND kernel codes Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* Merge branch 'fixes'Haavard Skinnemoen2009-01-22-7/+2
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| * avr32: Remove second definition of virt_to_phys()Haavard Skinnemoen2008-12-17-7/+2
| | | | | | | | | | | | | | | | | | | | The second definition introduced by 65e43a1063 conflicts with the existing one. Also, convert the existing definition to use phys_addr_t. The volatile qualifier is still needed due to brain damage elsewhere. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Prepare v2009.01v2009.01Wolfgang Denk2009-01-21-1/+11
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Prepare 2009.01-rc3v2009.01-rc3Wolfgang Denk2009-01-18-1/+177
| | | | | | | | | | | | Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-18-1/+1
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| * | fdt_resize(): fix actualsize calculations with unaligned blobsPeter Korsgaard2009-01-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in fdt_resize() to extend the fdt size to end on a page boundary is wrong for fdt's not located at an address aligned on a page boundary. What's even worse, the code would make actualsize shrink rather than grow if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), causing fdt_add_mem_rsv to fail. Fix it by aligning end address (blob + size) to a page boundary instead. For aligned fdt's this is equivalent to what we had before. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
* | | build system: treat all Darwin's alikeMike Frysinger2009-01-18-2/+2
|/ / | | | | | | | | | | | | The x86 based version of Darwin behaves the same quirky way as the powerpc Darwin, so only check HOSTOS when setting up Darwin workarounds. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | ncb: use socklen_tMike Frysinger2009-01-16-1/+1
| | | | | | | | | | | | The recvfrom() function takes a socklen_t, not an int. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-01-16-1083/+657
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| * | sh: serial: use readx/writex accessorsJean-Christophe PLAGNIOL-VILLARD2009-01-16-23/+23
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: serial: coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-17/+18
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Fix compile error on lowlevel_init fileNobuhiro Iwamatsu2009-01-16-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Fix up rsk7203 target for out of tree buildKieran Bingham2009-01-16-10/+19
| | | | | | | | | | | | | | | | | | | | | Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD2009-01-16-785/+338
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: lowlevel_init coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-634/+640
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: update sh2/sh2a timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: update sh timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-13/+13
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-01-16-163/+184
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| * | ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boardsMatthias Fuchs2009-01-14-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Disable pci node in device tree on CPCI405 pci adaptersMatthias Fuchs2009-01-14-0/+24
| | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Cleanup CPCI405 board codeMatthias Fuchs2009-01-14-163/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up CPCI405 board support: - wrap long lines - unification of spaces in function calls - remove dead code Use correct io accessors on peripherals. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Enable auto RS485 mode on PLU405 boardsMatthias Fuchs2009-01-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch turns on the auto RS485 mode in the 2nd external uart on PLU405 boards. This is a special mode of the used Exar XR16C2850 uart. Because these boards only have a 485 physical layer connected it's a good idea to turn it on by default. Signed-off-by: Matthias Fuchs <mf@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Prepare 2009.01-rc2v2009.01-rc2Wolfgang Denk2009-01-14-0/+588
| | | | | | | | | | | | | | | | | | Update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | cpu/mpc824x/Makefile: fix warning with parallel buildsWolfgang Denk2009-01-14-1/+1
|/ / | | | | | | | | | | | | | | | | | | Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-14-55/+67
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| * \ Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-14-13/+19
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| | * | Some changes of TLB entry setting for MPC8572DSHaiying Wang2009-01-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * | Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * | Change PCIE1&2 deciide logic on MPC8544DS board more readableRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bitRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | Fix IO port selection issue on MPC8544DS and MPC8572DS boardsRoy Zang2009-01-13-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | mpc8610hpcd: Fix PCI mapping conceptsBecky Bruce2009-01-13-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
| * | | sbc8641d: Fix PCI mapping conceptsBecky Bruce2009-01-13-23/+27
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* | | MPC86xx: fix build warningsWolfgang Denk2009-01-12-3/+1
|/ / | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-01-10-61/+93
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| * | bf537-stamp/nand: fix board_nand_init prototypeMike Frysinger2009-01-07-1/+3
| | | | | | | | | | | | | | | | | | The board_nand_init() function should return an int, not void. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: drop CONFIG_SPI handling in board initMike Frysinger2009-01-07-7/+0
| | | | | | | | | | | | | | | | | | | | | The eeprom SPI init functions are duplicated as the common code already executes these for us. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: fix out-of-tree building with ldscriptsMike Frysinger2009-01-07-16/+20
| | | | | | | | | | | | | | | | | | | | | Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: fix linker scripts to work with --gc-sectionsMike Frysinger2009-01-07-36/+48
| | | | | | | | | | | | | | | | | | | | | Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: set proper LDRFLAGS for parallel booting LDRsMike Frysinger2009-01-07-1/+22
| | | | | | | | | | | | | | | | | | | | | In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | at91rm9200: move define from lowlevel_init to headerJean-Christophe PLAGNIOL-VILLARD2009-01-06-48/+49
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | | m501sk: move to the common memory setupJean-Christophe PLAGNIOL-VILLARD2009-01-06-202/+33
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | | at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD2009-01-06-203/+203
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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