summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
...
| * | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-10-03-2/+2
| |\ \ | | |/ | |/|
| | * Blackfin: update default console= settingsMike Frysinger2009-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | | The Linux kernel has changed the way it numbers serial ports, so update the default command line to match it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | * Blackfin: bf533-ezkit: update env locationMike Frysinger2009-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The u-boot image has outgrown the current space and overflowed into the env sector. So move the env to the next available sector (we've already allocated the first few sectors anyways for u-boot). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armMinkyu Kang2009-10-12-2075/+4988
|\ \ \
| * \ \ Merge branch 't-next-marvell' into t-next-at91Tom Rix2009-10-04-0/+1
| |\ \ \
| | * | | arm: Correct build with CONFIG_SYS_HUSH_PARSER setSimon Kagstrom2009-10-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * | | | at91: Update MEESC board supportDaniel Gorsulowski2009-10-04-24/+66
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements several updates: -disable CONFIG_ENV_OVERWRITE -add new hardware style variants and set the arch numbers appropriate -pass the serial# and hardware revision to the kernel -removed unused macros from include/configs/meesc.h -fixed multiline comment style Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
| * | | TI: OMAP3: Overo Tobi ethernet supportOlof Johansson2009-10-04-33/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add setup for ethernet on Tobi, allowing kernel/ramdisk to be loaded over tftp. This also refactors the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
| * | | SMC911X: Add chip auto detectionOlof Johansson2009-10-04-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
| * | | TI OMAP3 Use arm init sequence to initialize i2cTom Rix2009-10-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes fixes an early i2c error. It appears that I2C is working because once a read or write error is detected, the omap24xx_i2c driver calls i2c_init inside its error handling check. While it is ok to attempt error handling this way, the boards must not depend on this side effect to initialize it's i2c. Instead of explicitly calling i2c_init for every board, use the generic arm initialization in lib_arm/board.c. By defining the config variable CONFIG_HARD_I2C, the omap3 i2c initialization is included in the init_sequence table. Run tested on Beagle. Compile tested on the omap3's Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
| * | | TI: DaVinci DM365: Enabling network Support on DM365 EVMSandeep Paulraj2009-10-04-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables EMAC on the DM365 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
| * | | TI: DaVinci: GPIO header file and definitionsSandeep Paulraj2009-10-04-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some DaVinci SOC's use GPIOs to enable EMAC and DM9000. This patch adds some definitions for GPIO registers and also adds structures for GPIO. A separate header file is being added so that in future we can have a DaVinci GPIO driver similer to OMAP. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
| * | | TI: DaVinci DM646x: Update flag used to represent DM646x SOC'sSandeep Paulraj2009-10-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the DaVinci specific code, we use both CONFIG_SOC_DM646X and CONFIG_SOC_DM646x to represent DM646x specific code. This patch changes occurrences of CONFIG_SOC_DM646x to CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use the flag CONFIG_SOC_DM644X. We want some uniformity. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
| * | | OMAP3: Clean up whitespace in mux configsOlof Johansson2009-10-04-1794/+1794
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch from space-based indentation to tab-based in mux configs, as pointed out by WD at: http://lists.denx.de/pipermail/u-boot/2009-September/061241.html Nothing but whitespace changes in this patch (diff -w gives no output). Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | OMAP3 MMC: Fix warning dereferencing type-punned pointerDirk Behme2009-10-04-27/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Steve Sakoman <sakoman@gmail.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
| * | | Merge branch 'arm/master' into arm/nextTom Rix2009-10-04-3282/+3952
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/AtmarkTechno/suzaku/Makefile board/amcc/acadia/acadia.c board/amcc/katmai/katmai.c board/amcc/luan/luan.c board/amcc/ocotea/ocotea.c board/cm-bf537u/Makefile board/cray/L1/L1.c board/csb272/csb272.c board/csb472/csb472.c board/eric/eric.c board/eric/init.S board/eukrea/cpuat91/Makefile board/exbitgen/exbitgen.c board/exbitgen/init.S board/freescale/mpc8536ds/config.mk board/g2000/g2000.c board/jse/sdram.c board/mpl/mip405/mip405.c board/mpl/pip405/pip405.c board/netstal/hcu5/hcu5.c board/netstal/mcu25/mcu25.c board/sc3/sc3.c board/w7o/init.S board/w7o/w7o.c common/cmd_reginfo.c cpu/ppc4xx/40x_spd_sdram.c cpu/ppc4xx/44x_spd_ddr.c doc/README.sbc8548 drivers/misc/fsl_law.c fs/ubifs/ubifs.c include/asm-ppc/immap_85xx.h Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * | | Support for the OpenRD base boardSimon Kagstrom2009-10-03-0/+691
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
| * | | Kirkwood: mv88f6281gtw_ge: Add kwbimage build supportPrafulla Wadaskar2009-10-03-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds kwbimage configuration file (used by mkimage utility) to support u-boot.kwb target on mv88f6281gtw_ge board. To create Kirkwood boot image to be flashed on SPI Flash, additional parameter u-boot.kwb need to be passed during make. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * | | Kirkwood: rd6281a: Add kwbimage build supportPrafulla Wadaskar2009-10-03-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds kwbimage configuration file (used by mkimage utility) to support u-boot.kwb target on rd6281a platform. To create Kirkwood boot image to be flashed on NAND, additional parameter u-boot.kwb need to be passed during make. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * | | Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-03-1/+900
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * | | Add support for Eukrea CPUAT91 SBCTom Rix2009-10-03-3/+702
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * | | mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]Wolfgang Denk2009-10-03-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | mucmc52, uc101: delete ata@3a00 node, if no CF card is detectedHeiko Schocher2009-10-03-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | mpc5200, mucmc52, uc101: config cleanupHeiko Schocher2009-10-03-504/+404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher <hs@denx.de> Minor edit of commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Fix "ppc/85xx: Clean up use of LAWAR defines" breakageWolfgang Denk2009-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_ defines were only enabled for the 83xx platform, but they are also needed on MPC512x system. Enabling these for E300 systems seems thus more appropriate. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Add Elpida Memory Configuration to mpc5121ads BoardsMartha M Stan2009-10-03-4/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-10-03-82/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-10-03-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala2009-10-03-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-10-03-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala2009-10-03-3/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala2009-10-03-18/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-10-03-11/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-10-03-20/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/85xx: Fix enabling of L2 cacheKumar Gala2009-10-03-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan2009-10-03-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/85xx: add cpu init config file for boot from NANDMingkai Hu2009-10-03-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | immap_85xx: add porpllsr's plat ratio definitionMingkai Hu2009-10-03-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/85xx: add ld script file for boot from NANDMingkai Hu2009-10-03-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc8610hpcd: Use common 86xx fdt fixup codePeter Tyser2009-10-03-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc85x0: tidy up Makefile to use new configuration script.Paul Gortmaker2009-10-03-29/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: allow enabling PCI via a make config optionPaul Gortmaker2009-10-03-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: update PCI/PCI-e support codePaul Gortmaker2009-10-03-143/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl_pci: create a SET_STD_PCI_INFO() helper wrapperPaul Gortmaker2009-10-03-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: correct local bus SDRAM size from 64M to 128MPaul Gortmaker2009-10-03-12/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: use I/O accessorsPaul Gortmaker2009-10-03-46/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: remove eTSEC3/4 voltage hackPaul Gortmaker2009-10-03-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: enable access to second bank of flashPaul Gortmaker2009-10-03-7/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | sbc8548: cosmetic line re-wrapPaul Gortmaker2009-10-03-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the extra long lines to be consistent with u-boot coding style. No functional change here. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * | | sbc8548: get_clock_freq is not valid for this boardPaul Gortmaker2009-10-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-10-19 13:19:20 +0000