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* Merge git://git.denx.de/u-boot-fdtTom Rini2016-01-22-1/+1
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| * devicetree: use wildcard to clean arch subdirThomas Chou2016-01-22-1/+1
| | | | | | | | | | | | | | | | Use wildcard to clean arch subdirectories, as it is cleaner than listing all the arch which builds dtb. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | rockchip: Update the READMESimon Glass2016-01-21-20/+20
| | | | | | | | | | | | | | | | | | | | GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC. There is an implementation to run the CPU at full speed although it does not seem to make much difference. Update the README to cover recent developments. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add support for Raxda Rock 2Simon Glass2016-01-21-6/+133
| | | | | | | | | | | | | | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: dts: Make changes for U-BootSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | Add the required pre-relocation tags and SDRAM init information for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: Bring in device tree files from LinuxSimon Glass2016-01-21-0/+458
| | | | | | | | | | | | | | Bring in the current device tree files for rock2 from linux/next commit 719d6c1. Hopefully this is the latest one. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: dts: Sync up SPDIF node with LinuxSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | | | This has been added and we have references to it in the rock2 board. Add this node. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: firefly-rk3288: Enable HDMI outputSimon Glass2016-01-21-1/+15
| | | | | | | | | | | | Enable HDMI output and a console on firefly. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Enable EDP and HDMI video outputSimon Glass2016-01-21-2/+18
| | | | | | | | | | | | | | | | | | | | | | Enable these devices using the VOPL video output device. We explicitly disable VOPB in the device tree to avoid it taking over. Since this device has an LCD display this comes up by default. If the display fails for some reason then it will attempt to use HDMI. It is possible to force it to fail (and thus fall back to HDMI) by puting 'return -EPERM' at the top of rk_edp_probe(). For now there is no easy way to select between the two. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Add support for timing SPI flash speedSimon Glass2016-01-21-0/+3
| | | | | | | | | | | | | | Add the 'time' and 'sf test' commands so that we can test SPI flash performance. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+124
| | | | | | | | | | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3288: pinctrl: Fix HDMI pinctrlSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | | | Since the device tree does not specify the EDID pinctrl option for HDMI we must set it manually. Fix the driver to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3288: clock: Fix various minor errorsSimon Glass2016-01-21-8/+13
| | | | | | | | | | | | Fix a number of small errors which were found in reviewing the clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Fix the SDRAM timingSimon Glass2016-01-21-1/+1
| | | | | | | | | | | | | | There is a minor error in the SDRAM timing. It does not seem to affect anything so far. Fix it just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spl: Drop MMC support code when not neededSimon Glass2016-01-21-2/+4
| | | | | | | | | | | | When the board does not use MMC SPL this code is a waste of space. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Tidy up the register-access macrosSimon Glass2016-01-21-3/+4
| | | | | | | | | | | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-21-14/+3
| | | | | | | | | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-21-2/+2
| | | | | | | | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: config: Enable the 'gpio' commandSimon Glass2016-01-21-0/+1
| | | | | | | | | | | | | | Now that we have a pretty good GPIO driver, enable the 'gpio' command on all rockchip boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add a script to parse datasheetsSimon Glass2016-01-21-0/+224
| | | | | | | | | | | | | | | | This script has proved useful for parsing datasheets and creating register shift/mask values for use in header files. Include it in case it is useful for others. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add a simple 'clock' commandSimon Glass2016-01-21-0/+24
| | | | | | | | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Don't skip low-level initSimon Glass2016-01-21-1/+8
| | | | | | | | | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a video-output driverSimon Glass2016-01-21-1/+696
| | | | | | | | | | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-1/+1722
| | | | | | | | | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+1408
| | | | | | | | | | | | | | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: Add support for clocks needed by the displaysSimon Glass2016-01-21-4/+170
| | | | | | | | | | | | | | The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-21-59/+38
| | | | | | | | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: video: Repurpose the 'displayport' uclass to 'display'Simon Glass2016-01-21-71/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DisplayPort uclass is too specific. The operations it provides are shared with other types of output devices, such as HDMI and LVDS LCD displays. Generalise the uclass so that it can be used with these devices as well. Adjust the uclass to handle the EDID reading and conversion to display_timing internally. Also update nyan-big which is affected by this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: panel: Add a simple panel driverSimon Glass2016-01-21-1/+100
| | | | | | | | | | | | | | | | Most panels are very simple - they just have a power supply and a backlight. Add a driver which supports this and implements the enable_backlight() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: panel: Add a panel uclassSimon Glass2016-01-21-0/+58
| | | | | | | | | | | | | | | | LCD panels can usefully be modelled as their own uclass. They can be probed (which powers them up ready for use). If they have a backlight, this can be enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: backlight: Add a driver for a PWM backlightSimon Glass2016-01-21-0/+137
| | | | | | | | | | | | | | Many backlights need to use a PWM to control the brightness. Add a driver for this. It understands the standard device tree binding. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: backlight: Add a backlight uclassSimon Glass2016-01-21-0/+58
| | | | | | | | | | | | | | | | LCD panels normally have a backlight which can be controlled to illuminate the LCD contents. Add a uclass to support this. Initially it only has a method to enable the backlight. Signed-off-by: Simon Glass <sjg@chromium.org>
* | pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-21-0/+154
| | | | | | | | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: pwm: Add a PWM uclassSimon Glass2016-01-21-0/+103
| | | | | | | | | | | | | | Add a uclass that supports Pulse Width Modulation (PWM) devices. It provides methods to enable/disable and configure the device. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: bridge: Allow GPIOs to be optionalSimon Glass2016-01-21-4/+7
| | | | | | | | | | | | | | Some video bridges will not have GPIOs to control reset, etc. Allow these to be optional. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Add a function to control cache flushingSimon Glass2016-01-21-0/+15
| | | | | | | | | | | | Allow the cache-flushing function of a video device to be controlled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Name consoles by their numberSimon Glass2016-01-21-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | We must use the console name in the 'stdout' variable to select the one we want. At present the name is formed from the driver name with a suffix indicating the rotation value. It seems better to name them sequentially since this can be controlled by driver order. So adjust the code to use 'vidconsole' for the first, 'vidconsole1' for the second, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* | gpio: Warn about invalid GPIOs used with the 'gpio' commandSimon Glass2016-01-21-1/+3
| | | | | | | | | | | | | | | | At present there is no indication that an invalid GPIO is used except that the GPIO status is not displayed. Make the error more explicit to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
* | stdio: Correct a build error with driver modelSimon Glass2016-01-21-0/+3
| | | | | | | | | | | | | | When driver model is used for video but not for the keyboard, a compiler warnings is produced. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Enable the Chrome OS ECSimon Glass2016-01-21-0/+28
| | | | | | | | | | | | Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Remove the explicit pinctrl settingSimon Glass2016-01-21-26/+2
| | | | | | | | | | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. The exception is when we want to use a different chip select (other than 0). But this isn't used at present. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Correct chip-enable codeSimon Glass2016-01-21-1/+6
| | | | | | | | | | | | | | | | At present there is an incorrect call to rkspi_enable_chip(). It should be disabling the chip, not enabling it. Correct this and ensure that the chip is disabled when releasing the bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Implement the delaysSimon Glass2016-01-21-4/+23
| | | | | | | | | | | | | | | | Some devices need delays before and after activiation. Implement these features in the SPI driver so that we will be able to enable the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: gpio: Implement the get_function() methodSimon Glass2016-01-21-4/+36
| | | | | | | | | | | | | | Provide this method so that 'gpio status' works fully. It now shows whether a pin is used for input, output or some other function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: gpio: Read the GPIO value correctlySimon Glass2016-01-21-1/+1
| | | | | | | | | | | | This function should return 0 or 1, not a mask. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: pinctrl: Implement the get_gpio_mux() methodSimon Glass2016-01-21-16/+52
| | | | | | | | | | | | | | Implement this so that the GPIO command will be able to report whether a GPIO is used for input or output. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: pinctrl: Reduce the size for SPLSimon Glass2016-01-21-3/+17
| | | | | | | | | | | | | | This file has many features that are not needed by SPL. Use #ifdef to remove the unused features and reduce the code size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2016-01-21-29/+30
| | | | | | | | | | | | | | | | | | | | | | | | The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Correct the bus init codeSimon Glass2016-01-21-2/+2
| | | | | | | | | | | | | | Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Remember the last speed to avoid re-setting itSimon Glass2016-01-21-1/+4
| | | | | | | | | | | | | | Rather than changing the clock to the same value on every transaction, remember the last value and don't adjust the clock unless it is necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 08:13:33 +0000