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* armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabledQianyu Gong2016-05-18-0/+5
| | | | | | | | | IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong2016-05-18-2/+25
| | | | | | | | | | The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-18-1/+1
| | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: Fix SCFG ICID reg addressesVincent Siles2016-05-18-2/+2
| | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Remove unnecessary flushing dcacheAlison Wang2016-05-18-3/+0
| | | | | | | | | As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: update eth primePrabhakar Kushwaha2016-05-18-2/+2
| | | | | | | | As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: enable sec_init in U-BootAneesh Bansal2016-05-18-0/+8
| | | | | | | | Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: update the node for QSPI supportYuan Yao2016-05-18-2/+3
| | | | | | | | The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* sf: Disable 4-KB erase command for SPANSION S25FS-S familyYuan Yao2016-05-18-0/+72
| | | | | | | | | | | | | | | | | The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-18-6/+57
| | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Assign AMBA mem according CS num in dtsYuan Yao2016-05-18-12/+43
| | | | | | | | | | | QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Fix issues on arm64Yuan Yao2016-05-18-19/+27
| | | | | | | | | | | The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fdt: add fixup_crypto_nodeAlex Porosanu2016-05-17-0/+19
| | | | | | | | | For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha2016-05-17-2/+2
| | | | | | | Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu2016-05-17-3/+3
| | | | | | | | | | | | | | Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+12
| | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-17-3/+10
| | | | | | | | Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-16/+49
| | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Prepare v2016.05Tom Rini2016-05-16-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* sunxi: Enable USB host in CHIP defconfigHans de Goede2016-05-15-0/+1
| | | | | | Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* test, tools: update tbot documentationHeiko Schocher2016-05-13-153/+103
| | | | | | | | update tbot documentation in U-Boot, as I just merged the event system into tbots master branch. Signed-off-by: Heiko Schocher <hs@denx.de>
* tests: py: fix NameError exception if bdi cmd is not supportedHeiko Schocher2016-05-13-0/+1
| | | | | | | | | | | | test/py raises an error, if a board has not enabled bdi command > pytest.skip('bdinfo command not supported') E NameError: global name 'pytest' is not defined import pytest in test/py/u_boot_utils.py fixes this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-12-21/+46
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* arm: socfpga: Update iomux and pll for c5 socdk RevEDinh Nguyen2016-05-10-36/+36
| | | | | | Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* warp7: Fix boot by selecting CONFIG_OF_LIBFDTFabio Estevam2016-05-10-0/+1
| | | | | | | | | | | | | | | | CONFIG_OF_LIBFDT needs to be selected to avoid the following boot problem: reading zImage 6346216 bytes read in 118 ms (51.3 MiB/s) Booting from mmc ... reading imx7d-warp.dtb 32593 bytes read in 11 ms (2.8 MiB/s) Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ] FDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ### Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-06-168/+90
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| * socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-06-1/+1
| | | | | | | | | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * mtd: cqspi: Simplify indirect read codeMarek Vasut2016-05-06-71/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect read code is a pile of nastiness. This patch replaces the whole unmaintainable indirect read implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. All the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. There is no speed change of the read operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
| * mtd: cqspi: Simplify indirect write codeMarek Vasut2016-05-06-96/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect write code is buggy pile of nastiness which fails horribly when the system runs fast enough to saturate the controller. The failure results in some pages (256B) not being written to the flash. This can be observed on systems which run with Dcache enabled and L2 cache enabled, like the Altera SoCFPGA. This patch replaces the whole unmaintainable indirect write implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. While this makes the patch look terrifying and violates all best-practices of software development, all the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
| * arm: socfpga: socrates: Add 'time' commandStefan Roese2016-05-06-0/+1
| | | | | | | | | | | | | | | | The time command is very helpful for performance and regressions tests. So lets enable it on SoCrates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
| * ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-05-06-13/+36
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| * | usb: gadget: dfu: discard dead codePeng Fan2016-05-06-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported by Coverity: Logically dead code (DEADCODE) dead_error_line: Execution cannot reach this statement: (f_dfu->strings + --i).s = .... If calloc failed, i is still 0 and no need to call free, so discard the dead code. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | dfu: avoid memory leakPeng Fan2016-05-06-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: dwc2: Add delay to fix the USB detection problem on SoCFPGAStefan Roese2016-05-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With patch c998da0d (usb: Change power-on / scanning timeout handling), the USB scanning is started earlier and with a smaller timeout. This resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not getting detected any more. This patch now adds a 1 second delay (in the host mode only) to the DWC2 driver before the scanning is started. With this delay, now all problematic USB keys are detected successfully again. And there is no need any more to change the delay / timeout in the common USB code (usb_hub.c). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: hub: Don't continue on get_port_status failureMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code shouldn't continue probing the port if get_port_status() failed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Assure Get Descriptor request is in separate microframeMarek Vasut2016-05-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kingston DT Ultimate USB 3.0 stick is sensitive to this first Get Descriptor request and if the request is not in a separate microframe, the stick refuses to operate. Add slight delay, which is enough for one microframe to pass on any USB spec revision. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Wait after sending Set Configuration requestMarek Vasut2016-05-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices, like the SanDisk Cruzer Pop need some time to process the Set Configuration request, so wait a little until they are ready. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Don't init pointer to zero, but NULLMarek Vasut2016-05-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pointer should always be inited to NULL, not zero (0). These are two different things and not necessarily equal. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: ehci-mx6: allow board_ehci_hcd_init to failStefan Agner2016-05-06-2/+5
| |/ | | | | | | | | | | | | | | | | | | | | There could be runtime determined board specific reason why a EHCI initialization fails (e.g. ENODEV if a Port is not available). In this case, properly return the error code. While at it, that function (board_ehci_hcd_init) has actually two documentation blocks... Use the correct function name for the documentation block of board_usb_phy_mode. Signed-off-by: Stefan Agner <stefan@agner.ch>
* | imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | test/py: dfu: wait for USB device to go away at bootStephen Warren2016-05-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | It can take a while for a host machine to notice that a USB device has disconnected, and process the change. At the end of the DFU test, we wait up to 10 seconds for this to happen. This change makes the test wait the same (up to) 10 seconds at the start of the test for any previously active USB device-mode session to be cleaned up. Such as session might have been used to download U-Boot into memory for example; this is certainly true on my Tegra test systems. This changes should solve the DFU test intermittency issues I've been seeing on some Tegra devices. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: am33xx: Fix DDR initialization delaysRuss Dill2016-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill@ti.com>
* | ARM: fix ifdefs in ARMv8 lowlevel_init()Stephen Warren2016-05-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the wrong endif was removed. This patch adds back that missing endif, and adds a new ifdef to match the endif the now-correctly-terminated block used to match against. Use "git show -U25 724219a65f55" to see enough context to make the original issue clear. In practical terms, this makes no difference to runtime behaviour. The code that was incorrectly compiled into the binary when ifndef MULTIENTRY is a no-op for other cases, since branch_if_master evaluates to a hard- coded jump. The only issues were: - A few extra instructions were added to the binary. - The comment on the endif at the very end of the function, indicating which ifdef it matched, were wrong. An alternative might be to simply fix the comment on that trailing ifdef, but that only addresses the second point above, not the first. Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* | mmc: Fix error in RPMB codeMarek Vasut2016-05-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we do not build any board with CONFIG_SUPPORT_EMMC_RPMB , this piece of code evaded conversion. Fix the following compiler error: cmd/mmc.c: In function 'do_mmcrpmb': cmd/mmc.c:316:32: error: 'struct blk_desc' has no member named 'part_num' original_part = mmc->block_dev.part_num; ^ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* | omap4: duovero: Disable EFI bootingAsh Charles2016-05-05-0/+1
| | | | | | | | | | | | | | | | The DuoVero board fails to compile with EFI enabled as the generated binaries are too large. As this platform doesn't currently need EFI, disable this feature. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* | omap4: load files for legacy bootAsh Charles2016-05-05-1/+4
|/ | | | | | | Be sure to load the zImage and fdtfile prior to actually booting in case we are doing a legacy boot. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* ARM: tegra: import latest Jetson TK1 spreadsheetStephen Warren2016-05-04-1/+14
| | | | | | | | | | | | | | | This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: tegra: fix DM conversion issues on Tegra20Stephen Warren2016-05-04-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra20's PCIe controller has a couple of quirks. There are workarounds in the driver for these, but they don't work after the DM conversion: 1) The PCI_CLASS value is wrong in HW. This is worked around in pci_tegra_read_config() by patching up the value read from that register. Pre-DM, the PCIe core always read this via a 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, so we need to check for offset 0x8 instead. Mask the offset value back to 32-bit alignment to make this work in all cases. 2) Accessing devices other than dev 1 causes a data abort. Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code called during enumeration while iterating over a bus. The DM PCIe core doesn't use this function. Instead, enhance tegra_pcie_conf_address() to validate the bdf being accessed, and refuse to access invalid devices. Since pci_skip_dev() isn't used, delete it. I've also validated that both these WARs are only needed for Tegra20, by testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in conditionally. Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-08 09:01:25 +0000