| Commit message (Collapse) | Author | Age | Lines |
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Only init the fastboot_dev and bootcmd env in the first boot
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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change the mx6dl/sabreauto u-boot prompt from SOLO to DL for better indication
Signed-off-by: Jason Liu <r64343@freescale.com>
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Fix build error when build Android
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The original design set the boot params default for eMMC on sabrsd
This patch corrects env setting according boot device which is selected.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Correct the recovery environment setting when boot from SD card on
sabresd board
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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To align with kernel display setting so that we may
avoid a blank interval during smooth UI transition
from uboot to Android desktop on LVDS0(LVDS1 is OK).
The code change refers to the following CR:
"ENGR00214565 MX6x, IPUv3: Display lack last horizontal
pixel"
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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To align with kernel display setting so that we may
avoid a blank interval during smooth UI transition
from uboot to Android desktop on LVDS0(LVDS1 is OK).
The code change refers to the following CR:
"ENGR00127358 ipuv3: make display data signal negative
during blanking period"
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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1. It is very useful to print the HAB event details
when the system is not closed to help debug issues
before blowing the fuse to secure the system.
2. Also need to authenticate a signed uImage in a open
system to help debug issues.
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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Align mx6q_sabreauto_nand config to other mx6q_* config
for command line buffer size
The buffer size is too short for dule display nand config
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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Add fastboot and recovery, add default
bootargs and bootcmd for Android.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Boot ROM fix the "glitchless mux" issue on TO1.2 which will mask
MMDC_CH0_MASK in CCM_CCDR, it will cause different behavior of
reset, need to clear this MMDC_CHx_MASK field to make sure
all the i.MX6 series SOCs have same behavior of reset.
Signed-off-by: Anson Huang <b20788@freescale.com>
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New thermal equation is working for all i.MX6 series
SOCs, so update it for i.MX6SL as well.
Signed-off-by: Anson Huang <b20788@freescale.com>
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mx6sl chip revision is from different-offset register in anatop module
comparing to other mx6 series. This patch fixes it and also uses board
'RevC' to indicate the latest board revision if this information can not
be obtained from fuse.
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 39e36b5e5a7cfe53fd6e286d9fe9024b365f1a29)
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Revert "ENGR00241595-4 mx6q-hdmidongle:Enable SATA PHY PDDQ default"
This reverts commit d33eefe083563a082840a46ec9cac21f98fad550.
Reasons:
* according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is
powered down automatically according to SATA controller
power mode SATA port support Disable/Slumber/Partial/Enabled(OOB)
The SATA PHY PDDQ mode is one-shot and recommeded to be used for test,
SATA would not work properly if the PHY PDDQ mode is enabled in U-boot.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Revert "ENGR00241595-3 mx6q-sabreauto:Enable SATA PHY PDDQ default"
This reverts commit 027af67a25773a0872659788eab0c09b72e2bbe0.
Reasons:
* according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is
powered down automatically according to SATA controller
power mode SATA port support Disable/Slumber/Partial/Enabled(OOB)
The SATA PHY PDDQ mode is one-shot and recommeded to be used for test,
SATA would not work properly if the PHY PDDQ mode is enabled in U-boot.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Revert "ENGR00241595-2 mx6q-arm2:Enable SATA PHY PDDQ default"
This reverts commit b10e0c4559602adacb22670506a1956a50cfd247.
Reasons:
* according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is
powered down automatically according to SATA controller
power mode SATA port support Disable/Slumber/Partial/Enabled(OOB)
The SATA PHY PDDQ mode is one-shot and recommeded to be used for test,
SATA would not work properly if the PHY PDDQ mode is enabled in U-boot.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Revert "ENGR00241595-1 mx6q-sabresd:Enable SATA PHY PDDQ default"
This reverts commit 9cb937432d1dc8d2c31afa5194f1ef0d8bdc0392.
Reasons:
* according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is
powered down automatically according to SATA controller
power mode SATA port support Disable/Slumber/Partial/Enabled(OOB)
The SATA PHY PDDQ mode is one-shot and recommeded to be used for test,
SATA would not work properly if the PHY PDDQ mode is enabled in U-boot.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Use universal equation and 25C's calibration data to
get thermal sensor's ratio on i.MX6DL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Use universal equation and 25C's calibration data to
get thermal sensor's ratio.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Quick fastboot just support download and flash commands.
Add reboot command support when launch fastboot by "fastboot q"
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Improvements for WEIM NOR read performance.
Changed burst and page size to 8 words.
Changed read wait states to 10 and page read wait states to 4.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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Currently, each board has one same function called get_mmc_env_devno,
this will make the code a little bit duplication. We can make the
get_mmc_env_devno to be a generic function, thus we can remove all the
scattered function definition in each board file.
And the patch also remove the boot check. Firstly, this check is needless,
secondly, this will break the second boot support,for example:
first boot from SPI, then switch to SD/MMC boot.
Signed-off-by: Jason Liu <r64343@freescale.com>
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MX6DQ and MX6DL share the common board file, but only MX6DQ has built-in
SATA, for the SATA PDDQ should be enabled default, so it needs to add
code to distinguish different chip ID.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Add partition table for nand boot.
Signed-off-by: b02247 <b02247@freescale.com>
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1. Correct oversight of setup and endpoint complete irq handler sequence
2. Add check to string descriptor index
Signed-off-by: LiGang <b41990@freescale.com>
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Add nand config for android sabreauto
Signed-off-by: b02247 <b02247@freescale.com>
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1. Add more check before writing image to storage
2. Fix failure when using nand storagea
Signed-off-by: LiGang <b41990@freescale.com>
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EPDC will be used when splash screen is shown, EPDC io setup is done
before 3V3 digitial power, which cause critical chip burn-out for all
platforms.
To follow the E-Ink specification, setup EPDC I/O after V3p3 is enable.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Remove mx6dl_arm2 and mx6dl_sabresd config file epdc macro
redefinition to avoid build warning.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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add MFG support for mx6solo sabresd board
Signed-off-by: Jason Liu <r64343@freescale.com>
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make system prompt indicate solo config when using mx6solo_sabresd:
"MX6Solo SABRESD U-Boot > "
Signed-off-by: Jason Liu <r64343@freescale.com>
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1. the new fastboot is an add-on feature, the original fastboot is reserved
2. the new fastboot is a subset of original fastboot, only support "download"
and "flash" command
3. type "fastboot" in uboot to launch the original fastboot utility,
type "fastboot q" in uboot to launch the new fastboot utility
Signed-off-by: LiGang <b41990@freescale.com>
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Add support for Processor UID ATAG in uboot for iMX53. The UID is
present in Fuses bank 0 at offset 0x20.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Support fastboot and recovery
Signed-off-by: b02247 <b02247@freescale.com>
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Update DDR script of ARD solo emulation, the ddr script
based on the following commit from ddr-scripts-rel git:
dfde48e Added MX6Solo ARD DDR3 init.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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This patch update the DDR script for mx6solo_sabresd board. The DDR script
based on the following commit from ddr-scripts-rel.git
9d4e11a Added MX6Solo SabreSD DDR3 script
Signed-off-by: Jason Liu <r64343@freescale.com>
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PFDs need to be gate/ungate after PLL lock to reset
PFDs to right state. Otherwise PFDs may lose correct
state in state-machine, then no output clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396
already since the bus clock needs it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add support for Android fastboot and recovery reboot
commands for iMX5.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This issue due to PODF is not used correcly, need use the following instead:
ACLK_EMI_SLOW_PODF_OFFSET, the original used ACLK_EMI_PODF_OFFSET was wrong.
Signed-off-by: Jason Liu <r64343@freescale.com>
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The issue is caused by DDR script changed io pads to DDR differential mode
but forget to do the calibration data update.
This patch updated the DDR script on MX6DL ARD board based on
the commit on the ddr-scripts-rel:
53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new
calibration values for IO pads set to differential mode;
Signed-off-by: Jason Liu <r64343@freescale.com>
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The original plugin code uses hard coded assembly address for the code jump
to "pu_irom_hwcnfg_setup", it can only works for specific chip version, for
a new TO, the assembly address will change, and the plugin code simply fails.
In fact there is an API entry table in a fixed ROM location, it contains the
entry to the "pu_irom_hwcnfg_setup". This patch retrieve the jump address
from this API table, thus avoid the limitation for current implementation.
Apply to all plugin enabled platforms, MX6Q/DL ARM2, MX6SL ARM2/EVK
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Add HDMIdongle board for imx6Q/DL under board/freescale.
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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Aligning the flash header to remove the boot plugin as in previous release.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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This commit update the DDR script for i.MX6Q sabresd board
based on the top of the following commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
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* Remove EIM_A24 nor pads as this are used for
io steer control and are not connectted to NOR
flash memory.
* Fix conflict access when it's used as io control
gpio.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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