summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* x86: Drop unused copy_fdt_to_ram()Simon Glass2015-08-05-19/+0
| | | | | | | | This is now handled by generic U-Boot code so we do not need an x86 version. It is no-longer called, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up global_data flagsSimon Glass2015-08-05-7/+11
| | | | | | | | | | These flags now overlap some global ones. Adjust the x86-specific flags to avoid this. Since this requires a change to the start.S code, add a way for tools to find the 32-bit cold reset entry point. Previously this was at a fixed offset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Reserve the top 16 flag bits for architecture-specific useSimon Glass2015-08-05-1/+1
| | | | | | | | | Add a convention that the generic global_data only occupy the bottom 16 bits of the flags word, so that there is less chance of a conflict. At present the x86 flags conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use CR0 constants in CPU initSimon Glass2015-08-05-1/+1
| | | | | | | We should use these constants where possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add various minor tidy-ups to the 32-bit startup codeSimon Glass2015-08-05-20/+26
| | | | | | | | Fix a typo, improve some comments and add a little more detail in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Bring in __aligned_u64 and friends to linux/types.hSimon Glass2015-08-05-1/+5
| | | | | | | | These will be used for efi.h both for U-Boot running as an EFI application and as a payload. They come from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Allow objcopy to work without filling gaps with 0xffSimon Glass2015-08-05-3/+7
| | | | | | | | | This is currently done for all targets, since 0xff is the default erased value for most flash devices. In some cases this is not what we want (e.g. for EFI images) so provide a command to do a vanilla objcopy. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* elf: Add a few definitions for 64-bit relocationSimon Glass2015-08-05-0/+26
| | | | | | | Provide the types necessary to relocate 64-bit images. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: serial: Correct logic in serial_find_console_or_panic()Simon Glass2015-08-05-1/+1
| | | | | | | | | | | | | In a final attempt to find a console UART this function uses the first first available serial device. However the check for a valid device is inverted. This code is only executed when there is in fact no serial UART, but at present it can fail to reach the panic_str() call in this case, and start trying to use a non-existent UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Check for empty list in uclass_find_device()Simon Glass2015-08-05-0/+2
| | | | | | | | This function needs to check the list has entries before traversing it. Fix this bug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Support removing default assembler flagsSimon Glass2015-08-05-1/+2
| | | | | | | | | | The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be removed for particular files. Add the same feature for assembler, using AFLAGS_REMOVE_<file>. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: command add '\n' for debug msgPeng Fan2015-08-05-1/+1
| | | | | | | | | | Add '\n' for debug msg. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* lib: fdt: fix indent of #ifdef..#endif conditionalMasahiro Yamada2015-08-05-1/+1
| | | | | | | | Match the depth of indentation between #ifdef and #endif for better readability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* common: Print nothing in the __weak checkboard()Bin Meng2015-08-05-1/+0
| | | | | | | Do not print confusing "Board: Unknown" during boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* gitignore: Add defconfig and fdtgrepBin Meng2015-08-05-0/+2
| | | | | | | Ignore defconfig and tools/fdtgrep. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+74
| | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-1/+283
| | | | | | | | Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add microcode for BayTrail-I B0 steppingBin Meng2015-08-05-0/+4244
| | | | | | | | This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-05-1/+2
| | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Remove smsc47x superio codesBin Meng2015-08-05-14/+0
| | | | | | | | | On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Sanity test on vesa parameters before setting up kernel screen_infoBin Meng2015-08-05-0/+4
| | | | | | | | We should not set up kernel screen_info when the vesa parameters are insane, otherwise kernel will panic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add MP initializationBin Meng2015-08-05-0/+21
| | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add a 'pause' instruction in __udelay() for QEMU targetMiao Yan2015-08-05-0/+8
| | | | | | | | | | | | | | | | When running SMP configuration on QEMU (tcg mode, no kvm), there is a busy loop in start_aps(), calling udelay(), that waits for APs to show up online. However, there is a chance that VCPU1 will be timeout waiting, IOW the secondary VCPUs haven't started their execution yet. This patch adds a 'pause' instruction in __udelay() only for QEMU target, to give other VCPUs a chance to run. When QEMU sees the 'pause' instruction, it will yeild the execution to other CPUs. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* doc: dm: Update pci-info.txt for pci supportBin Meng2015-08-05-3/+3
| | | | | | | Correct two typos and mention how pci bus will be probed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow scan bridge child devices before relocationBin Meng2015-08-05-4/+0
| | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. Remove such limitation so that dm pci can be used before relocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-08-04-432/+1185
|\
| * armv8/ls2085ardb: Add USB support for ls2085ardbNikhil Badola2015-08-03-0/+13
| | | | | | | | | | | | | | Add USB XHCI support for ls2085rdb platform Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Add USB support for ls2085aqdsNikhil Badola2015-08-03-0/+13
| | | | | | | | | | | | | | Add USB XHCI support for ls2085qds platform Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-03-0/+3
| | | | | | | | | | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-03-0/+1
| | | | | | | | | | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/ddr/fsl: Adjust bstopre valueYork Sun2015-08-03-6/+8
| | | | | | | | | | | | | | | | | | By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helperhoria.geanta@freescale.com2015-08-03-9/+8
| | | | | | | | | | | | Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: fix snooping for write transactionshoria.geanta@freescale.com2015-08-03-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: fix "era" property value on LE platformshoria.geanta@freescale.com2015-08-03-2/+1
| | | | | | | | | | | | | | | | | | | | Use fdt_setprop_u32() instead of fdt_setprop(). Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node") Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/pci/layerscape: Add EP mode supportMinghuan Lian2015-08-03-2/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch will initialize PCIe controller on EP mode 1. Setup bar: bar0 32bit 4K for specific configuration bar1 32bit 8K for MSIX bar2 64bit 4K for descriptor of memory bar4 64bit 1M for DMA memory test 2. Setup iATU: iATU inbound 0-3 to map bar transaction to memory address started at CONFIG_SYS_PCI_EP_MEMORY_BASE iATU outbound 0 to map 4G memory space Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/pci: Add function to find an extended capabilityMinghuan Lian2015-08-03-0/+94
| | | | | | | | | | | | | | | | | | | | PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: flib changes for mc 8.0.0Prabhakar Kushwaha2015-08-03-221/+571
| | | | | | | | | | | | | | | | | | MC firware version 8.0.0 contains new command flags. This patch contains modifications in FLIB files to support the new command flags. Signed-off-by: Itai Katz <itai.katz@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: enable raw data instead of von Neumann dataAlex Porosanu2015-08-03-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: change starting entropy delay valueAlex Porosanu2015-08-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process. This patch changes the starting value of the length of the entropy sample to 3200 system clocks. In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: disable RNG oscillator maximum frequency checkAlex Porosanu2015-08-03-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds. This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a/etsec: Enable Tx Data and TxBD snoopingAlison Wang2015-08-03-4/+0
| | | | | | | | | | | | | | | | | | To improve eTSEC performance on LS1021A Rev2.0, snooping of all transmit frames from memory and all transmit BD memory accesses in enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: allow OCRAM access permission as R/W in SPLAlison Wang2015-08-03-171/+184
| | | | | | | | | | | | | | | | | | On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin tableWang Dongsheng2015-08-03-0/+8
| | | | | | | | | | | | | | | | | | | | | | Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021atwr: program the regulator for deep sleepchenhui zhao2015-08-03-0/+34
| | | | | | | | | | | | | | | | Program the external regulator to switch off voltage in deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021atwr: added deep sleep support in ubootTang Yuantian2015-08-03-4/+75
| | | | | | | | | | | | Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/lS1021atwr: Enable bootscript for secure bootgaurav rana2015-08-03-0/+1
| | | | | | | | | | | | | | | | Enable bootscript support in secure boot for establishing chain of trust on LS1021atwr. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/qe: use strncpy instead of strcpyZhao Qiang2015-08-03-1/+1
| | | | | | | | | | | | | | strncpy is safer than strcpy, use it to instead of strcpy. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/qe: transform parameter to compatible typeZhao Qiang2015-08-03-2/+3
| | | | | | | | | | | | | | | | when using printf, the parameter type need to be compatible type, so transform them to compatible type Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: Reserve secure code into RAM instead of OCRAMZhuoyu Zhang2015-08-03-2/+0
| | | | | | | | | | | | | | | | | | For ls1021a, Reserve secure code in to memory in case OCRAM is needed by other usage. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | configs: ti_armv7_keystone2: replace addr_uboot with loadaddrVitaly Andrianov2015-08-03-3/+3
|/ | | | | | | | | This patch replaces not existing addr_uboot environment variable by loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these commands are broken. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
generated by cgit v1.1 at 2024-11-10 12:41:15 +0000