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| * | | board: k2e_evm: add network supportHao Zhang2014-10-23-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds network support code and enables keystone_net driver usage for k2e_evm evaluation board. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone: clock: add support for K2E SoCsKhoronzhuk, Ivan2014-10-23-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For K2E and K2L SoCs clock output from PASS PLL has to be enabled after NETCP domain and PA module are enabled. So create new function for that and call it after PA module is enabled. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: increase PHY auto negotiate timeKhoronzhuk, Ivan2014-10-23-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time to auto negotiate with SoC's SGMII port. It can take about 3 sec to up the PHY after reset, so add code to expose sgmii auto negotiation waiting process. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: add Keystone2 K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone2 Edison SoC uses the same keystone net driver. This patch adds opportunity to use it by K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_serdes: add keystone K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: keysonte_nav: add support for K2E SoCKhoronzhuk, Ivan2014-10-23-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone navigator, but uses different NETCP PktDMA definitions. This patch adds required definitions. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: use general get link functionKhoronzhuk, Ivan2014-10-23-46/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy framework has function to get link, so use it instead of own implementation. There is no reason to check SGMII link while sending each packet, phy link is enough. Check SGMII link only while ethernet open. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: register eth PHYs on MDIO busKhoronzhuk, Ivan2014-10-23-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: register MDIO busKhoronzhuk, Ivan2014-10-23-38/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MDIO framework is not used to configure Ethernet PHY. As result some of already implemented functions are duplicated. So register MDIO bus in order to use it. On that stage it's just registered, it'll be used as we start to use PHY framework. Use mdio bus read/write/reset functions in the driver. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: use mdio_reset functionKhoronzhuk, Ivan2014-10-23-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use mdio_enable twice while eth open. Also rename it to keystone2_mdio_reset as more appropriate name. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: phy: print a number of phy that is not foundKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: generalize configuration mechanismKhoronzhuk, Ivan2014-10-23-47/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cmu, comlane, lane configuration mechanism are similar for sub systems as well such as PCI or sRIO, but they have different values based on input clock and output bus rate. According to this compact driver to simplify adding different configuration settings based on clock and rate. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: generalize to be used by other sub systemsHao Zhang2014-10-23-42/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurationsHao Zhang2014-10-23-82/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-23-138/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: remove redundant code from keystone_net.cKhoronzhuk, Ivan2014-10-23-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused tx_send_loop variable. Removes duplicated get_link_status() call from the keystone2_eth_send_packet(). The emac_gigabit_enable() is called at opening Ethernet and there is no need to enable it on sending each packet. So remove that call from keystone2_eth_send_packet() as well. The calling of power/clock up functions are mostly the responsibility of SoC/board code, so move these functions to appropriate place. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: increase MDIO clock frequencyVitaly Andrianov2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With MAC_PHY sgmii configuration, u-boot checks PHY link status before sending each packet. Increasing MDIO frequency increases overall tftp speed. We set it to maximum 2.5MHz. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: move header file from arch to ti-commonKhoronzhuk, Ivan2014-10-23-260/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: add support for NETCP v1.5Khoronzhuk, Ivan2014-10-23-62/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the network driver is used only by k2hk evm board. The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e contain NETCP v1.5. So driver should be able to work with such kind of NETCP. This commit adds this opportunity. The main difference in masks and some registers, the logic is the same, so only definitions should be changed. To differentiate between versions add KS2_NETCP_V1_0 and KS2_NETCP_V1_5. Also remove unused and no more needed defines. The port number is specific for each board so move this parameter to configuration. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: remove SoC specific emac_regs structureHao Zhang2014-10-23-20/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | configs: ks2_evm: enable misc_init_rKhoronzhuk, Ivan2014-10-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently keystone has misc_init_r where all DSPS are turned off by default. So enable this function. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: k2l-evm: add board supportHao Zhang2014-10-23-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone II Lammar (K2L) EVM board support. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: enable OSR clock domain for K2L SoCHao Zhang2014-10-23-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches enables the On-chip Shared Ram clock domain for K2L SoC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: spl: move board specific codeHao Zhang2014-10-23-66/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization of PLLs is a part of board specific code, so move it appropriate places. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: msmc: add MSMC cache coherency support for K2L SOCHao Zhang2014-10-23-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: clock: add K2L clock definitions and commandsHao Zhang2014-10-23-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock definitions and commands to support Keystone II K2L SOC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: add K2L device hardware definitionsHao Zhang2014-10-23-2/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware definitions specific to Keystone II Lamar (K2L) SoC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: cmd_clock: generalize command usage descriptionKhoronzhuk, Ivan2014-10-23-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usage description of commands refers to headers of sources, that is not correct. This patch is intended to fix it. Also generalize code in order to reduce SoC dependent #ifdefs. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone: usb: add support of usb xhciWingMan Kwok2014-10-23-1/+379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-89/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan2014-10-23-29/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: keystone_nav: don't use hard addresses in netcp_pktdmaKhoronzhuk, Ivan2014-10-23-29/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use definitions in netcp_pktdma instead direct addresses. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: keystone_nav: don't use hard addresses in qm_configKhoronzhuk, Ivan2014-10-23-32/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use definitions in qm_config. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-10-27-43/+37
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| * | | arm: socfpga: config: Add USB support exampleMarek Vasut2014-10-27-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add example configuration stub for the DWC2 USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de>
| * | | tools/socfpgaimage.c: fix build on darwinAndreas Bießmann2014-10-27-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | socfpgaimage utilizes htole32 and friends, unfortunately these functions are not available on darwin. Fix it by using the cpu_to_le32 and friends defined in compiler.h as other parts in mkimage do. This patch fixes the following error: ---8<--- HOSTCC tools/socfpgaimage.o tools/socfpgaimage.c:77:22: warning: implicit declaration of function 'htole32' is invalid in C99 [-Wimplicit-function-declaration] header.validation = htole32(VALIDATION_WORD); ^ tools/socfpgaimage.c:80:22: warning: implicit declaration of function 'htole16' is invalid in C99 [-Wimplicit-function-declaration] header.length_u32 = htole16(length_bytes/4); ^ tools/socfpgaimage.c:95:6: warning: implicit declaration of function 'le32toh' is invalid in C99 [-Wimplicit-function-declaration] if (le32toh(header.validation) != VALIDATION_WORD) ^ tools/socfpgaimage.c:97:6: warning: implicit declaration of function 'le16toh' is invalid in C99 [-Wimplicit-function-declaration] if (le16toh(header.checksum) != hdr_checksum(&header)) ^ 4 warnings generated. ... HOSTLD tools/dumpimage Undefined symbols for architecture x86_64: "_htole16", referenced from: _socfpgaimage_set_header in socfpgaimage.o "_htole32", referenced from: _socfpgaimage_set_header in socfpgaimage.o "_le16toh", referenced from: _verify_buffer in socfpgaimage.o "_le32toh", referenced from: _verify_buffer in socfpgaimage.o ld: symbol(s) not found for architecture x86_64 --->8--- Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Zap CONFIG_EPHY[01]_PHY_ADDR macroMarek Vasut2014-10-27-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not used anywhere, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Zap spl.h and ad-hoc related symsMarek Vasut2014-10-27-31/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Move code from misc_init_r() to arch_early_init_r()Marek Vasut2014-10-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization code should be executed much earlier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
* | | | Merge http://git.denx.de/u-boot-sunxiTom Rini2014-10-26-80/+1010
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| * | | | sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig optionHans de Goede2014-10-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5 "p" value to 1 (divide by 2) as that is what those kernels are hardcoded too, in the future this may enable further workarounds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@ti.com> -- Changes in v2: -s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT. -Move the code block setting P(1) for old kernels to where P gets cleared
| * | | | sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcodingHans de Goede2014-10-24-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Add clock_get_pll5p() functionHans de Goede2014-10-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)Ian Campbell2014-10-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * | | | ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfigChen-Yu Tsai2014-10-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same. See: http://linux-sunxi.org/Ippo_q8h Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add support for using R_UART as consoleChen-Yu Tsai2014-10-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads. Add support for R_UART so we can have a console while using mmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Allow specifying module in prcm apb0 init functionChen-Yu Tsai2014-10-24-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add support for R_PIO gpio banksHans de Goede2014-10-24-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add basic A23 supportChen-Yu Tsai2014-10-24-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup. There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-10-01 19:27:05 +0000