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* | socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See2014-08-29-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | socfpga: fix clock manager register definitionPavel Machek2014-08-29-101/+107
| | | | | | | | | | | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
* | arm: include config.h in arch/arm/lib/vectors.SChristian Riesch2014-08-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
* | ARM:asm:io.h use static inlineJeroen Hofstee2014-08-29-6/+6
|/ | | | | | | | | | | When compiling u-boot with W=1 the extern inline void for read* is likely causing the most noise. gcc / clang will warn there is never a actual declaration for these functions. Instead of declaring these extern make them static inline so it is actually declared. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-08-29-392/+679
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| * pcm051: use ti_am335x_common.h configMatwey V. Kornilov2014-08-25-136/+4
| | | | | | | | | | | | Include general configs/ti_am335x_common.h and drop redundant #defines. Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
| * ARM: DRA: Enable VTT regulatorLokesh Vutla2014-08-25-0/+36
| | | | | | | | | | | | | | | | | | | | DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * am335x_evm: Convert CONFIG_CONS_INDEX into a menu choiceTom Rini2014-08-25-43/+27
| | | | | | | | | | | | | | | | | | | | - Drop CONFIG_SERIAL[1-6] and use CONFIG_CONS_INDEX tests instead - Add choice and help text to board/ti/am335x/Kconfig - Correct comment about IDK in board/ti/am335x/mux.c - Remove am335x_evm_uart* defconfig files as they're just variations on a config option now. Signed-off-by: Tom Rini <trini@ti.com>
| * cm-t54: convert to generic boardDmitry Lifshitz2014-08-25-0/+3
| | | | | | | | | | | | | | Use generic board setup functions by defining CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * cm-t54: fix eMMC boot mode checkDmitry Lifshitz2014-08-25-1/+1
| | | | | | | | | | | | | | | | | | | | Boot from eMMC boot partition corresponds to BOOT_DEVICE_MMC2 omap_bootmode, while BOOT_DEVICE_MMC2_2 corresponds to the user data partition boot. Fix mmc_get_env_part() boot mode check to use a correct value. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * cm-t54: fix EEPROM read return value checkDmitry Lifshitz2014-08-25-2/+2
| | | | | | | | | | | | | | Fix cl_eeprom_read_mac_addr() return value check. Fix long line codding style issue in board_init(). Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * ARM: DRA7: Enable software leveling for dra7Sricharan R2014-08-25-68/+32
| | | | | | | | | | | | | | | | | | | | Currently hw leveling is enabled by default on DRA7/72. But the hardware team suggested to use sw leveling as hw leveling is not characterized and seen some test case failures. So enabling sw leveling on all DRA7 platforms. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * SOM: tam3517: convert to generic boardJeroen Hofstee2014-08-25-0/+1
| | | | | | | | | | | | Cc: Raphael Assenat <raph@8d.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * keystone2: use EFUSE_BOOTROM information to configure PLLsVitaly Andrianov2014-08-25-8/+173
| | | | | | | | | | | | | | | | | | This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * board/ti/dra7xx: add support for parallel NORpekon gupta2014-08-25-8/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
| * board/ti/dra7xx: add support for parallel NANDpekon gupta2014-08-25-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select[0] on DRA7xx EVM. As GPMC pins are shared by multiple devices, so in addition to this patch following board settings are required for NAND device detection [1]: SW5.9 (GPMC_WPN) = OFF (logic-1) SW5.1 (NAND_BOOTn) = ON (logic-0) /* Active-low */ SW5.2 (NOR_BOOTn) = OFF (logic-1) SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations SW2.1 (SYSBOOT[0]) = ON (logic-1) /* selects NAND Boot */ SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */ SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */ SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */ SW2.5 (SYSBOOT[4]) = ON (logic-1) /* selects NAND Boot */ SW2.6 (SYSBOOT[5]) = ON (logic-1) /* selects NAND Boot */ SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */ SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */ SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */ SW3.5 (SYSBOOT[12])= ON (logic-1) /* device type: Addr/Data Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Following changes are required in board.cfg to enable NAND on J6-EVM:
| * board/ti/am43xx: add support for parallel NANDpekon gupta2014-08-25-1/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NAND device connected to GPMC chip-select on following AM43xx EVM boards. am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a time either eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled by: (a) Statically using Jumper on connecter (J89) present on board. (a) If Jumper on J89 is NOT used, then selection can be dynamically controlled by driving SPI2_CS0[MUX_MODE=GPIO] pin via software: SPI2_CS0 == 0: NAND (default) SPI2_CS0 == 1: eMMC am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI, Thus only one of the two can be used at a time. Selection is controlled by: (a) Dynamically driving following GPIO pin from software GPMC_A0(GPIO) == 0 NAND is selected (default) NAND device (MT29F4G08AB) on these boards has: - data-width=8bits - blocksize=256KB - pagesize=4KB - oobsize=224 bytes For above NAND device, ROM code expects the boot-loader to be flashed in BCH16 ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * board/ti/am335x: add support for beaglebone NOR Capepekon gupta2014-08-25-60/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support of NOR cape[1] for both Beaglebone (white) and Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC chip-select[0] and accesses as external memory-mapped device. This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device. As GPMC chip-select[0] can be shared by multiple capes so NOR profile is not enabled by default in boards.cfg. Following changes are required to enable NOR cape detection when building am335x_boneblack board profile. Signed-off-by: Tom Rini <trini@ti.com>
| * board/ti/am335x: add support for beaglebone NAND capepekon gupta2014-08-25-20/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64 (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2] * How to boot from NAND using Memory Expander + NAND Cape ? * - Important: As BOOTSEL values are sampled only at POR, so after changing any setting on SW2 (DIP switch), disconnect and reconnect all board power supply (including mini-USB console port) to POR the beaglebone. - Selection of ECC scheme for NAND cape(a), ROM code expects BCH8_HW ecc-scheme for NAND cape(b), ROM code expects BCH16_HW ecc-scheme - Selction of boot modes can be controlled via DIP switch(SW2) present on Memory Expander cape. SW2[SWITCH_BOOT] == OFF follow default boot order MMC-> SPI -> UART -> USB SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2) So to flash NAND, first boot via MMC or other sources and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape. - For NAND boot following switch settings need to be followed SW2[ 1] = OFF (SYSBOOT[ 0]==1: NAND boot mode selected ) SW2[ 2] = OFF (SYSBOOT[ 1]==1: -- do -- ) SW2[ 3] = ON (SYSBOOT[ 2]==0: -- do -- ) SW2[ 4] = ON (SYSBOOT[ 3]==0: -- do -- ) SW2[ 5] = OFF (SYSBOOT[ 4]==1: -- do -- ) SW2[ 6] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device ) SW2[ 7] = ON (SYSBOOT[ 9]==0: ECC done by ROM ) SW2[ 8] = ON (SYSBOOT[10]==0: Non Muxed device ) SW2[ 9] = ON (SYSBOOT[11]==0: -- do -- ) [1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion [2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module *IMPORTANT NOTE* As Beaglebone board shares the same config as AM335x EVM, so following changes are required in addition to this patch for Beaglebone NAND cape. (1) Enable NAND in am335x_beaglebone board profile (2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because: - AM335x EVM has NAND device with datawidth=8, whereas - Beaglebone NAND cape has NAND device with data-width=16
| * board/ti/am335x: update configs for parallel NANDpekon gupta2014-08-25-24/+29
| | | | | | | | | | | | | | | | | | | | This patch - consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various configuration files into single file. - update MTD Partition table to match AM335x_EVM DT in linux-kernel - segregate CONFIGs based on different boot modes (like SPL and U-Boot) Signed-off-by: Pekon Gupta <pekon@ti.com>
| * am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOTTom Rini2014-08-25-0/+1
| | | | | | | | | | | | | | When we're using EMMC_BOOT that means we have environment on eMMC so we can make use of CONFIG_SPL_ENV_SUPPORT within Falcon Mode. Signed-off-by: Tom Rini <trini@ti.com>
| * common/Makefile: Consolidate SPL ENV options, correct inclusionTom Rini2014-08-25-7/+5
| | | | | | | | | | | | | | CONFIG_SPL_NET_SUPPORT is not the only time we want SPL to ahve environment, CONFIG_SPL_ENV_SUPPORT is when we want it. Signed-off-by: Tom Rini <trini@ti.com>
| * tseries: Set CONFIG_ENV_IS_NOWHERE for SPL+NANDTom Rini2014-08-25-1/+5
| | | | | | | | | | | | | | | | | | In the case of SPL on these boards we only need environment for SPL_USBETH, so it's safe to normally use ENV_IS_NOWHERE and SPL+NAND does not support environment today. Cc: Hannes Petermaier <oe5hpm@oevsv.at> Signed-off-by: Tom Rini <trini@ti.com>
| * TI:armv7: Change CONFIG_SPL_STACK to not be CONFIG_SYS_INIT_SP_ADDRTom Rini2014-08-25-8/+11
| | | | | | | | | | | | | | | | | | | | There are times where we may need more than a few kilobytes of stack space. We also will not be using CONFIG_SPL_STACK location prior to DDR being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick a good location within DDR for this to be. Tested on OMAP4/AM335x/OMAP5/DRA7xx. Signed-off-by: Tom Rini <trini@ti.com>
| * am335x_evm: Move SPL network definesTom Rini2014-08-25-9/+4
| | | | | | | | | | | | | | | | On am335x_evm we only support USBETH for a networking SPL option so move the rest of the defines under that area as that's the only time we need (and want) environment support here. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge git://git.denx.de/u-boot-usbTom Rini2014-08-29-5/+25
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| * | usb: hub: don't check CONNECTION in hub_port_reset()Stephen Warren2014-08-29-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One specific USB 3.0 device behaves strangely when reset by usb_new_device()'s call to hub_port_reset(). For some reason, the device appears to briefly drop off the bus when this second bus reset is executed, yet if we retry this loop, it'll eventually come back after another two resets. If USB bus reset is executed over and over within usb_new_device()'s call to hub_port_reset(), I see the following sequence of results, which repeats as long as you want: 1) STAT_C_CONNECTION = 1 STAT_CONNECTION = 0 USB_PORT_STAT_ENABLE 0 2) STAT_C_CONNECTION = 1 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 0 3) STAT_C_CONNECTION = 1 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1 The device in question is a SanDisk Ultra USB 3.0 16GB memory stick with USB VID/PID 0x0781/0x5581. In order to allow this device to work with U-Boot, ignore the {C_,}CONNECTION bits in the status/change registers, and only use the ENABLE bit to determine if the reset was successful. To be honest, extensive investigation has failed to determine why this problem occurs. I'd love to know! I don't know if it's caused by: * A HW bug in the device * A HW bug in the Tegra USB controller * A SW bug in the U-Boot Tegra USB driver * A SW bug in the U-Boot USB core This issue only occurs when the device's USB3 pins are attached to the host; if only the USB2 pins are connected the issue does not occur. The USB3 controller on Tegra is in reset, so is not actively communicating with the device at all - a USB3 analyzer confirms this. Slightly unplugging the device (so the USB3 pins don't contact) or using a USB2 cable or hub as an intermediary avoids the problem. For some reason, the Linux kernel (either on the same Tegra board, or on an x86 host) has no issue with the device, and I observe no disconnections during reset. This change won't affect any USB device that already works, since such devices could not currently be triggering the error return this patch removes, or they wouldn't be working currently. However, this patch is quite reliable in practice, hence I hope it's acceptable to solve the problem. The only potential fallout I can see from this patch is: * A broken device that triggers C_CONNECTION/!CONNECTION now causes the loop in hub_port_reset() to run multiple times. If it never succeeds, this will cause "usb start" to take roughly 1s extra to execute. * If the user unplugs a device while hub_port_reset() is executing, and very quickly swaps in a new device, hub_port_reset() might succeed on the new device. This would mean that any information cached about the original device (from the descriptor read in usb_new_device(), which simply caches the max packet size) might be invalid, which would cause problems talking to the new device. However, without this change, the new device wouldn't work anyway, so this is probably not much of a loss. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: Handle -ENODEV from usb_lowlevel_init()Marek Vasut2014-08-29-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we support both Host and Device mode operation, an OTG controller can return -ENODEV on a port which it found to be in Device mode during Host mode scan for devices. In case -ENODEV is returned, print that the port is not available and continue instead of screaming a bloody error message. Signed-off-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-08-29-20/+5
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| * | | ARM: zynq: Remove spl.hMichal Simek2014-08-19-18/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not specify own zynq specific SPL macros because there is no need for that. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: zynq: Move ps7_init() out of spl.hMichal Simek2014-08-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | zynq: spl: Add vectors section to linker scriptPeter Crosthwaite2014-08-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vectors section contains the _start symbol which is used as the program entry point. Add it to the linker script in same fashion as done for regular u-boot. This allows for correct generation of an spl elf with a non-zero entry point. A similar change was applied to sunxi platform in "sunxi: Fix u-boot-spl.lds to refer to .vectors" (sha1: 9e5f80d823e3fd2a685b10ecf02009e34b86cff9) This also allows for placement of the vector table at the hivecs location by setting the TEXT_BASE to 0xffff0000. Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2014-08-29-10/+745
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| * | | | ARM: tegra: remove custom define for Jetson TK1Stephen Warren2014-08-19-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that Kconfig has a per-board option, we can use that directly rather than inventing a custom define for the AS3722 code to determine which board it's being built for. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: add Colibri T30 board supportStefan Agner2014-08-18-0/+612
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds board support for the Toradex Colibri T30 module. Working functions: - SD card boot - eMMC environment and boot - USB host/USB client (on the dual role port) - Network (via ASIX USB) Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: Use mem size from MC rather than ODMDATAStephen Warren2014-08-18-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In at least Tegra124, the Tegra memory controller (MC) has a register that controls the memory size. Read this to determine the memory size rather than requiring this to be redundantly encoded into the ODMDATA. This way, changes to the BCT (i.e. MC configuration) automatically updated SW's view of the memory size, without requiring manual changes to the ODMDATA. Future work potentially required: * Clip the memory size to architectural limits; U-Boot probably doesn't and won't support either LPAE or Tegra's "swiss cheese" memory layout, at least one of which would be required for >2GB RAM. * Subtract out any carveout required by firmware on future SoCs. Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: enable DFU tooStephen Warren2014-08-18-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DFU protocol support (via the "dfu" command) on Tegra boards where USB device/gadget mode is enabled. Note that for DFU to operate correctly on Tegra, we still need some DFU fixes/enhancements that are going through the DFU -> USB trees. However, the code builds just fine without those changes, and applying this patch now will allow both sets of patches to meet in the main U-Boot tree much more quickly. In order to run test/dfu/dfu_gadget_test.sh, you would need to add the following to the board configuration: CONFIG_EXT4_WRITE CONFIG_CMD_EXT4_WRITE However, I haven't enabled those here, since I believe the main use-case for DFU on Tegra is raw flash writing, rather than filesystem access, so we don't need the additional code-size hit. However, I could be persuaded otherwise! We should probably add a separate test script for raw flash access. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: Disable VPRBryan Wu2014-08-18-0/+97
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-08-29-205/+6001
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| * | | | mx6sxsabresd: Add Ethernet supportFabio Estevam2014-08-20-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031. Add support for one FEC port initially. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | mx6sx: Adjust enable_fec_anatop_clock() for mx6soloxFabio Estevam2014-08-20-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure and enable the ethernet clock for mx6solox. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | mx6sxsabresd: Convert to the new Kconfig styleFabio Estevam2014-08-20-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sxsabresd was not in the master branch when the conversion to the new Kconfig style happened, so convert it now so that it can build again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | imx: ventana: add econfig commandTim Harvey2014-08-20-86/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Gateworks Ventana EEPROM contains a set of configuration bits that affect the removal of device-tree nodes that support peripherals that do not exist on sub-loaded boards. This patch adds: - a structure to define a config bit name, dt node alias, bit position - an array of supported configuration items - an econfig command to get/set/list configuration bits - use of the array when adjusting the FDT prior to boot Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: leave PCI reset de-asserted if PCI enabledTim Harvey2014-08-20-5/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: add iomux for PCISKT_WDIS# gpioTim Harvey2014-08-20-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCISKT_WDIS# gpio allows for asserting WDIS# going to the various PCIe sockets on the Ventana board. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: enable SION bit on gpio outputsTim Harvey2014-08-20-63/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the SION bit on gpio outputs that we wish to be able to read the value of. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: configure i2c_dis# pin properly for gw53xxTim Harvey2014-08-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i2c_dis# pinmux/padconf was missing for the GW53xx (this feature was added to the GW53xx on revB PCB's). Additionally, remove the duplicate config for GW54xx. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: add missing crlf to printTim Harvey2014-08-20-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: add video enable gpio pinmux for GW54xxTim Harvey2014-08-20-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | | | imx: ventana: add appropriate delay following GSC i2c writeTim Harvey2014-08-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Gateworks System Controller EEPROM config is flash based. Add a delay following writes to avoid errors on back-to-back writes. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
generated by cgit v1.1 at 2024-10-31 19:33:41 +0000