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* mx6qsabreauto: Staticize when possibleFabio Estevam2014-09-16-8/+8
| | | | | | Turn all local symbols into static in order to make sparse happy. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sxsabresd: Staticize i2c_pad_info1Fabio Estevam2014-09-16-1/+1
| | | | | | | | | | i2c_pad_info1 is only used locally, so it can be made static. Fix the following sparse warning: board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDRPeng Fan2014-09-16-1/+1
| | | | | | | Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC2_BASE_ADDR which is used in board_mmc_init. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDRPeng Fan2014-09-16-1/+1
| | | | | | | | | | | Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR. USDHC3 and USDHC4 are both initialized in board_mmc_init. There is no restriction on USDHC3 addr or USDHC4 addr should be assigned to CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid errors when fsl_esdhc_mmc_init is invoked. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDRPeng Fan2014-09-16-1/+1
| | | | | | | | | | | Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used in board_mmc_init. If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to correct value. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: vf610: add NAND support for vf610twrStefan Agner2014-09-16-5/+93
| | | | | | | | | | | This adds NAND support for the Vybrid tower system (TWR-VF65GS10) provided by the vf610_nfc driver. Full 16-Bit bus width is supported. Also an aditional config vf610twr_nand is introduced which gets the environment from NAND. However, booting U-Boot from NAND is not yet possible due to missing boot configuration block (BCB). Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: nand: add Freescale vf610_nfc driverStefan Agner2014-09-16-0/+725
| | | | | | | | | | This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* arm: mx35: use common timer functionsAndrew Ruder2014-09-16-83/+12
| | | | | | | | | | | | | | | | | This patch moves mx35 to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) mx35 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx35 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* arm: mx31: use common timer functionsAndrew Ruder2014-09-16-102/+12
| | | | | | | | | | | | | | | | | | | | This patch moves mx31 to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) mx31 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx31 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Helmut Raiger <helmut.raiger@hale.at>
* imx: mx6slevk: Change to use generic boardYe.Li2014-09-11-0/+2
| | | | | | Enable CONFIG_SYS_GENERIC_BOARD for imx6slevk to use generic board. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6q/dlarm2: Change to use generic boardYe.Li2014-09-11-0/+2
| | | | | | | Enable the CONFIG_SYS_GENERIC_BOARD for imx6q/dl arm2 board to use generic board. Signed-off-by: Ye.Li <B37916@freescale.com>
* README.imximage: Fix the maximum DCD sizeFabio Estevam2014-09-11-1/+1
| | | | | | | | | | In commit 021e79c85371 ("tools: imximage: Fix the maximum DCD size for mx53/mx6") we have fixed the maximum DCD size for mx53/mx53. Do the same on the README document for consistency. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Fix build of mx6sxsabresdStefano Babic2014-09-11-1/+1
| | | | | | | | | | Commit 224beb833e544b802f08765271cec07667d39669 add clock enabling function for FEC, but the masks are not available for SX processor and the mx6sxsabresd cannot be built clean. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Nikita Kiryanov <nikita@compulab.co.il>
* mx6sxsabresd: Add PCI supportFabio Estevam2014-09-09-0/+10
| | | | | | | | | | | | | | | | | Tested with an Intel Wireless PCI 7260HMW card: U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11) CPU: Freescale i.MX6SX rev1.0 at 792 MHz Reset cause: WDOG Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-8/+58
| | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6qsabreauto: Remove imx6q-sabreauto.dtsFabio Estevam2014-09-09-17/+0
| | | | | | | | | | | | | | Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced 'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains the 'model' and 'compatible' strings. After this commit the final binary is also changed from 'u-boot.imx' to 'u-boot-dtb.imx', which may confuse users. So revert it until a more complete and useful device tree could be provided. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx: nitrogen6x: Replace 'fatload' by 'load' command in env settings to be ↵Guillaume GARDET2014-09-09-3/+3
| | | | | | | | | | | | filesystem independent nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic 'load' command instead of 'fatload'. It allows to use ext filesystem and keep compatibilty with fat filesystem. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Stefano Babic <sbabic@denx.de> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
* mx6dlsabresd: Use its own DCD tableFabio Estevam2014-09-09-1/+132
| | | | | | | | | Currently mx6dlsabresd shares the same DCD settings with the nitrogen board. Provide a DCD configuration file specific to mx6dlsabresd with the settings recommended by the Freescale hardware team. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-09-0/+10
| | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
* arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-09-6/+3
| | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-09-4/+4
| | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* imximage: Fix imximage IVT bug for EIM-NOR bootYe.Li2014-09-09-0/+7
| | | | | | | | | | | The load region size of EIM-NOR are defined to 0. For this case, the parameter "imximage_init_loadsize" must be calculated. The imximage tool implements the calculation in the "imximage_generate" function, but the following function "imximage_set_header" resets the value and not calculate. This bug cause some fields of IVT head are not correct, for example the boot_data and DCD overlay the application area. Signed-off-by: Ye.Li <B37916@freescale.com>
* iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-09-0/+3
| | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
* imx: ventana: Avoid undefined behaviourThierry Reding2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
* tools: imximage: Fix the maximum DCD size for mx53/mx6Fabio Estevam2014-09-09-1/+1
| | | | | | | | | | | | | | | According to mx53 and mx6 reference manuals: "The maximum size of the DCD limited to 1768 bytes." As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and excluding the first entry, which is the header leads to 220 as the maximum number for DCD size. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
* imx: ventana: add pci fixup for PLX PEX860x switch GPIOTim Harvey2014-09-09-0/+31
| | | | | | | | Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion. These boards use GPIO on the PLX device as PERST# for the downstream ports thus we assert this when the PLX is enumerated. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-09-0/+11
| | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* arm: mx6: cm_fx6: add sata supportNikita Kiryanov2014-09-09-0/+134
| | | | | | | | | Add support for SATA. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm_fx6: use eepromNikita Kiryanov2014-09-09-0/+32
| | | | | | | | | | Use Compulab eeprom module to obtain revision number, serial number, and mac address from the EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm_fx6: add i2c supportNikita Kiryanov2014-09-09-0/+53
| | | | | | | | | | Add support for all 3 I2C busses on Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm_fx6: add usb supportNikita Kiryanov2014-09-09-0/+89
| | | | | | | | | Add USB and USB OTG host support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm_fx6: add ethernet supportNikita Kiryanov2014-09-09-2/+115
| | | | | | | | | | Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm_fx6: add nand supportNikita Kiryanov2014-09-09-1/+78
| | | | | | | | | | Add NAND support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: add support for Compulab cm-fx6 CoMNikita Kiryanov2014-09-09-0/+819
| | | | | | | | | | | | | Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov2014-09-09-3/+1
| | | | | | | | | | | | | | | | Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov2014-09-09-0/+1
| | | | | | | | | | | | | | | | According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
* arm: mx6: ddr: do not write into reserved bitNikita Kiryanov2014-09-09-1/+1
| | | | | | | | | Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: ddr: cleanupNikita Kiryanov2014-09-09-141/+137
| | | | | | | | | No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov2014-09-09-0/+18
| | | | | | | | | | | | Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* compulab: eeprom: add support for defining eeprom i2c busNikita Kiryanov2014-09-09-1/+15
| | | | | | | | | | | | | | | Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+95
| | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* imx: ventana: added cputype env varTim Harvey2014-09-09-0/+1
| | | | | | | | There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: add GW5520 supportTim Harvey2014-09-09-7/+81
| | | | | | | | | | | The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as: * 2x MiniPCIe sockets * 2x USB host sockets * 2x i210 GigE * HDMI out * digital I/O expansion Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: base SPL MMDC calibration on width and size not boardTim Harvey2014-09-09-80/+109
| | | | | | | | | | | | | | The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: updated notes regarding NAND boot errataTim Harvey2014-09-09-2/+3
| | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
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