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* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-01-22-1126/+128
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| * ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2Masahiro Yamada2015-01-23-0/+44
| | | | | | | | | | | | PH1-sLD3, PH1-LD6b have DDR channel 2. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: rename SG_MEMCONF_* macros for readabilityMasahiro Yamada2015-01-23-20/+20
| | | | | | | | | | | | | | Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined by <linux/sizes.h> for readability. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: use <linux/sizes.h> for readabilityMasahiro Yamada2015-01-23-12/+13
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: remove non-sense inline directivesMasahiro Yamada2015-01-23-6/+6
| | | | | | | | | | | | | | | | The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: add static to local functionsMasahiro Yamada2015-01-23-15/+15
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: fix IECTRL set code for PH1-Pro4Masahiro Yamada2015-01-23-1/+1
| | | | | | | | | | | | | | | | For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: describe init_page_table shorterMasahiro Yamada2015-01-23-1069/+26
| | | | | | | | | | | | | | | | | | The assembly directive ".rept ... .endr" allows us to write the init_page_table much shorter. To make things further simpler, set the text and stack area as Normal Memory, and the other sections as Device attribute. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: fix comments in SoC Glue init functionMasahiro Yamada2015-01-23-2/+2
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: remove __packed that causes a problem on GCC 4.9Masahiro Yamada2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR PHY training function, ddrphy_prepare_training() would not work if compiled with GCC 4.9. The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h) is specified with __packed because it represents a hardware register mapping, but it turned out to cause a problem on GCC 4.9. If -mno-unaligned-access is specified (yes, it is in arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the __attribute__((packed)) and generates extra instructions to perform the memory access in a way that does not cause unaligned access. (Actually it is not need here because the register base, the first argument of the ddrphy_prepare_training(), is always given with a 4-byte aligned address.) Anyway, as a result, readl() / writel() is divided into byte-wise accesses. The problem is that this hardware only accepts 4-byte register access. Byte-wise accesses lead to unexpected behavior. There are some options to avoid this problem. [1] Remove -mno-unaligned-access [2] Add __aligned(4) along with __packed to struct ddrphy [3] Remove __packed from struct ddrphy [1] solves the problem for ARMv7, but it does not for pre-ARMv6 and ARMv6-M architectures where -mno-unaligned-access is default. So, [1] does not seem reasonable in terms of code portability. Both [2] and [3] work well, but [2] seems too much. All the members of struct ddrphy have the u32 type. No padding would be inserted even if __packed is dropped. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-01-22-123/+206
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| * | MIPS: add support for pre-relocation mallocDaniel Schwierzeck2015-01-21-4/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement MIPS specific setup of the gd_t structure to support pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified, a memory area will be reserved after the initial stack area and the gd->malloc_base pointer will be initialized. After this patch the new driver model can be used on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: add support for CONFIG_SYS_INIT_SP_ADDRDaniel Schwierzeck2015-01-21-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | Support the existing config option CONFIG_SYS_INIT_SP_ADDR on MIPS. This allows to move the initial stack to other places than the beginning of RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: add Kconfig option for CONFIG_SWAP_IO_SPACEDaniel Schwierzeck2015-01-21-2/+4
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: replace $(CPU) with Kconfig symbolsDaniel Schwierzeck2015-01-21-2/+12
| | | | | | | | | | | | | | | | | | | | | Conditionally set head-y and lib-y with boolean Kconfig symbols for selected CPU. This deprecates the usage of the $(CPU) variable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: use common code from lib/time.cThomas Langer2015-01-21-110/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The common code just needs the C0_COUNT as free running counter, without the need of writing and checking C0_COMPARE. The function get_tbclk() is still implemented here instead of changing all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE. The change was tested on a MIPS32 system, but as the MIPS64 code was/is the same, this should be no problem. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
| * | MIPS: bootm: add bootstage reportingDaniel Schwierzeck2015-01-21-2/+6
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: bootm: prepare a flattened device tree for the kernelDaniel Schwierzeck2015-01-21-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial code to prepare a flattened device tree for the kernel like relocating the FDT blob and fixing up the /chosen and /memory nodes. The final hand over to the kernel is not yet implemented. After the community agreed on the MIPS boot interface for device trees, the corresponding code will be added. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: bootm: add mem, rd_start and rd_size to kernel command lineDaniel Schwierzeck2015-01-21-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | If the user wants to boot a kernel without legacy environment, information like memory size, initrd address and size should be handed over to the kernel in the command line. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: bootm: refactor preparation of Linux kernel environmentDaniel Schwierzeck2015-01-21-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | Move preparation of Linux kernel environment in a separate function and mark it as legacy. Add a Kconfig option to make that legacy mode configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: bootm: refactor preparation of Linux kernel command lineDaniel Schwierzeck2015-01-21-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | Move preparation of Linux kernel command line in a separate function and mark it as legacy. Add a Kconfig option to make that legacy mode configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | Merge branch 'next' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-22-1/+5
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| * | | microblaze: Support stack protection featureMichal Simek2015-01-21-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that stack didn't rewrite important part of u-boot. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Enable hardware exception by defaultMichal Simek2015-01-21-1/+1
| |/ / | | | | | | | | | | | | | | | | | | Enable hardware exception by default to be able to handle it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'phys_t' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-22-7/+9
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| * | | mmc: zynq: Use phys_addr_t for addressesMichal Simek2015-01-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | phys_addr_t is designed for physical addresses that's why use it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: ll_temac: Fix compilation warning because of phys_addr_tMichal Simek2015-01-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the compilation warning w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init': w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects argument of type 'unsigned int', but argument 4 has type 'phys_addr_t' [-Wformat] introduced by "net: Declare physical address as phys_addr_t unsigned type" (sha1: 16ae7827226ce8b255245d1932e8069f00997a26). Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: gem: Use phys_addr_t instead of int for addressesMichal Simek2015-01-21-3/+5
| |/ / | | | | | | | | | | | | | | | | | | Use phys_addr_t for physical address declaration. It is also unsigned type instead of sign. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-22-67/+158
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| * | fpga: zynqpl: Add support for zc7035Siva Durga Prasad Paladugu2015-01-21-0/+10
| | | | | | | | | | | | | | | | | | | | | Added support for zc7035 Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: Show fpga info if definedMichal Simek2015-01-21-4/+5
| | | | | | | | | | | | | | | | | | | | | Show fpga_op->info even if desc->iface_fns is not defined. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | fpga: xilinx: Check if fpga operations are definedMichal Simek2015-01-21-2/+15
| | | | | | | | | | | | | | | | | | | | | Ensure that operations are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | fpga: xilinx: zynqpl: Setup NULL fpga_op without driverMichal Simek2015-01-21-6/+17
| | | | | | | | | | | | | | | | | | | | | Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: virtex2: Fix macro indentationMichal Simek2015-01-21-4/+4
| | | | | | | | | | | | | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: virtex2: Setup NULL fpga_op without driverMichal Simek2015-01-21-14/+31
| | | | | | | | | | | | | | | | | | | | | Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: spartan3: Setup NULL fpga_op without driverMichal Simek2015-01-21-14/+31
| | | | | | | | | | | | | | | | | | | | | Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: spartan2: Setup NULL fpga_op without driverMichal Simek2015-01-21-11/+27
| | | | | | | | | | | | | | | | | | | | | Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: Export fpga_get_desc for SPLMichal Simek2015-01-21-1/+2
| | | | | | | | | | | | | | | | | | | | | SPL needs to detect FPGA device which will be used for loading bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: Remove extern prototypes from .hMichal Simek2015-01-21-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | This problem is reported by checkpatch.pl Warnings: CHECK: extern prototypes should be avoided in .h files Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: Protect GZIP usage when LOADMK is enabledMichal Simek2015-01-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For case where CMD_FPGA_LOADMK is enabled and GZIP disable. Warning log: common/built-in.o: In function `do_fpga': /mnt/disk/u-boot/common/cmd_fpga.c:218: undefined reference to `gunzip' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sunxi: Restore lowlevel_init usageHans de Goede2015-01-21-22/+21
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2 recent sunxi changes have removed the usage of lowlevel_init by moving some code around and then setting CONFIG_SKIP_LOWLEVEL_INIT. This is problematic for 2 reasons: 1) It does not just stop s_init from being called, it also stops cpu_init_cp15 from getting called, which is undesirable. 2) We want u-boot.bin to be usable standalone, without SPL, some people e.g. use an upstream u-boot.bin together with Allwinner's boot0 loader. So u-boot.bin must (re)initialize the gpios, timer, etc. This commit restores the lowlevel_init / s_init usage, while keeping the changes to no longer use the global-data (gd) struct in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-arcTom Rini2015-01-20-71/+123
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| * | arc: rename "arc700" in "arcv1"Alexey Brodkin2015-01-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a preparation to ARCv2 port submission we rename "arc700" folder to "arcv1" which stands for ARCv1 ISA also known as ARCompact. This will allow us to add more flavours of binary-compatible ARCv1 CPUs like ARC600 if needed later on and all required ARCv2 CPUs (which are binary incompatible with ARCv1) in "arcv2" folder in subsequent commits. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * | board/synopsys: remove selection of CPU from the boardAlexey Brodkin2015-01-15-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | Both ARCangel4 and AXS10x are FPGA-based boards so they may have different CPUs. For now we have only 1 option (ARC700) and we define this as default in arch Kconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | arc: move common sources in libraryAlexey Brodkin2015-01-15-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * | arc: move linker script in arch/arc/cpu folderAlexey Brodkin2015-01-15-0/+0
| | | | | | | | | | | | | | | | | | This way we'll be able to use the same one script for either ARC CPU. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | arc: relocate - minor refactoring and clean-upAlexey Brodkin2015-01-15-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | arc: introduce separate section for interrupt vector tableIgor Guryanov2015-01-15-31/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * | arc: add dependences on MMU presenceAlexey Brodkin2015-01-15-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on MMU presence in CPU there're differences in HW behavior. For example address of instruction that caused exception is put in ECR register if MMU exists and in ERET register otherwise. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * | arc: interrupts - fix mask setupIgor Guryanov2015-01-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To disable interrupts we need to reset corresponding flags in STATUS32 register. For this we need to OR flags for interrupts level1 and level2 and then AND with current value in STATUS32. Before that implementation was incorrect. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
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