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| * | | config: peach: Correct memory layout environment settingsSjoerd Simons2015-04-06-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The peach boards have their SDRAM start address at 0x20000000 instead of 0x40000000 which seems common for all other exynos5 based boards. This means the layout set in exynos5-common.h causes the kernel be loaded more then 128MB (at 0x42000000) away from memory start which breaks booting kernels with CONFIG_AUTO_ZRELADDR Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses the same offsets from start of memory as the common exynos5 settings. This fixes booting via bootz and PXE Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos5: add trace feature #ifdef in exynos5-common.hInha Song2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can enable / disable trace feature from the FTRACE config options. To enable, compile U-Boot with FTRACE=1. This patch add #ifdef FTRACE in exynos5-common.h for enable/disable to use FTRACE configs instead of having to change board config files. Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | sunxi: Fix Orangepi_mini dtb filenameHans de Goede2015-04-04-1/+16
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Orangepi_mini is different enough from the regular Orangepi that it needs its own dtb, but when it got added a copy and paste error was made and it got the same dtb filename, fix this. While at it also add a short description of both Orangepi boards to the defconfig files for them. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | Merge git://git.denx.de/u-boot-arcTom Rini2015-04-03-583/+602
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| * | | board: AXS10x - update SDIO clock valueAlexey Brodkin2015-04-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the most recent board firmware correct SDIO clock is 50MHz as opposed to 25 MHz before. Also set max frequency of MMC data exchange equal to SDIO clock - because there's no way to transfer data faster than interface clock. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: add support for SLC (System Level Cache, AKA L2-cache)Alexey Brodkin2015-04-03-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | board: Switch Abilis TB-100 board to Driver Model for serial portAlexey Brodkin2015-04-03-5/+31
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| * | | serial-arc: switch to DMAlexey Brodkin2015-04-03-32/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now when all infrastructure in ARC is ready for it let's switch ARC UART to driver model. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| * | | arc: minor fixes in KconfigAlexey Brodkin2015-04-03-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line lenth selection is correctly enabled if either I$ or D$ are enabled. [2] Add dummy entry to target list to make sure target type is always mentioned in defconfig. Otherwise defconfig for the first target in the list will not have target name and later on with addition of the new target on top of the list in Kconfig will lead to corrupted configuration expanded from defconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATAAlexey Brodkin2015-04-03-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed on mailing list we're drifting away from CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem() for global data. So do this for ARC architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: re-generate defconfigsAlexey Brodkin2015-04-03-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before that moment our defconfigs were manually modified with addition of new options. That means once anybody wants to add another option and re-genarate defconfig with "make defconfig" there will be lots of differences. So to make future modifications more clean we'll do bulk re-generation right away. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: clean-up init procedureAlexey Brodkin2015-04-03-81/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intention behind this work was elimination of as much assembly-written code as it is possible. In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc. It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86. Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
| * | | arc: move low-level interrupt and exception handlers in a separate fileAlexey Brodkin2015-04-03-144/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This separation makes maintenance of code easier because those low-level interrupt- or exception handling routines are pretty static and usually require not much care while start-up code is a subject of modifications and enhancements. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: merge common start-up code between ARC and ARCv2Alexey Brodkin2015-04-03-294/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ARCompact and ARCv2 are not binary compatible most of assembly instructions are used in both. With this change we'll get rid of duplicate code. Still IVTs are implemented differently so we're keeping them in separate files. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: cache - build invalidate_icache_all() and invalidate_dcache_all()Alexey Brodkin2015-04-03-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | always Make both invalidate_icache_all() and invalidate_dcache_all() available even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or CONFIG_SYS_ICACHE_OFF. This is useful because configuration of U-Boot may not match actual hardware features. Real board may have cache(s) but for some reason we may want to run U-Boot with cache(s) disabled (for example if some peripherals work improperly with existing drivers if data cache is enabled). So board may start with cache(s) enabled (that's the case for ARC cores with built-in caches) but early in U-Boot we disable cache(s) and make sure all contents of data cache gets flushed in RAM. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | serial/serial_arc: set registers address during compilationAlexey Brodkin2015-04-03-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Being global variable with 0 value it falls into .bss area which we may only use after relocation to RAM. And right afetr relocation we zero .bss - effectively cleaing register address set for early console. Now with pre-set value "regs" variable is no longer in .bss and this way safely survives relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-109/+247
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | ARM: tegra: colibri_t20: fix nand pinmuxMarcel Ziswiler2015-03-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pingroup ATC seems to come out of reset with config set to NAND, so we need to explicitly configure some other function to this group in order to avoid clashing settings. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BITLucas Stach2015-03-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: update colibri_t20 configurationMarcel Ziswiler2015-03-30-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring the Colibri T20 configuration in-line with Apalis/Colibri T30. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: fix colibri_t20 asix resetMarcel Ziswiler2015-03-30-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ASIX USB to Ethernet chip reset. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: fix colibri_t20 machine typeMarcel Ziswiler2015-03-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: rename colibri_t20 board/configuration/device-treeMarcel Ziswiler2015-03-30-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: get rid of colibri_t20-commonMarcel Ziswiler2015-03-30-57/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a preparatory step to renaming the board folder as well first get rid of the colibri_t20-common after having integrated it into colibri_t20_iris for now. While at it also migrate to using NVIDIA's common.mk magic. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: seaboard: Correct the gpio_request() callSimon Glass2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Requesting a GPIO without a name is not supposed anymore. This causes the request to fail. Add a name so that the serial console works on seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIOSimon Glass2015-03-30-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CONFIG is not used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: enable MIPI PAD CTRL support for Tegra124Stephen Warren2015-03-30-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: pinctrl: add support for MIPI PAD control groupsStephen Warren2015-03-30-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: pinctrl: minor cleanupStephen Warren2015-03-30-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: pinctrl: move Tegra210 code to the correct dirStephen Warren2015-03-30-0/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARMv8: enable DM in vexpress64 boardDavid Feng2015-03-27-1/+25
| | | | | | | | | | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
| * | ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-6/+11
| | | | | | | | | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | | Prepare v2015.04-rc5Tom Rini2015-03-31-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-456/+673
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| * | | ARM: at91: sama5: move the common part of configurations to at91-sama5_common.hWu, Josh2015-04-01-298/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a new configuration file: at91-sama5_common.h. Which includes the configurations that reused by all SAMA5 chips. at91-sama5_common.h includes: - hw macros (clock, text_base and etc.) - default commands. - BOOTARGS - U-Boot common configs. NOTE: NOR flash definition should be put before including the common header. For sama5d3-xplained: - add CMD_SETEXPR For sama5d3xek: - add CMD_SETEXPR - change CONFIG_SYS_MALLOC_LEN to (4*1024*1024) Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * | | ARM: atmel: at91sam9n12ek: enable spl supportBo Shen2015-04-01-5/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9n12ek boards, now it supports boot up from NAND flash, serial flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | | ARM: atmel: at91sam9x5ek: enable spl supportBo Shen2015-04-01-4/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | | ARM: atmel: at91sam9m10g45ek: enable spl supportBo Shen2015-04-01-1/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | | ARM: atmel: arm926ejs: fix clock configurationBo Shen2015-04-01-26/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed. Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Heiko Schocher <hs@denx.de>
| * | | ARM: at91: at91sam9n12ek: save the environment to a fat file in MMC cardWu, Josh2015-04-01-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Insteading in mmc's raw sectors, this patch will save the environment in a fat file (uboot.env) in mmc card's first FAT patition by default. If you want to save in mmc's raw sectors, you only need to define CONFIG_ENV_IS_IN_MMC. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
| * | | ARM: at91: atmel_nand: Support flash based BBTDavid Dueck2015-04-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on-flash bad block table. This makes U-Boot handle an existing BBT correctly. Signed-off-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Andreas Bießmann <andreas.devel@googlemail.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: Josh Wu <josh.wu@atmel.com>
| * | | arm, at91: corvus: move MACH_TYPE to defconfigHeiko Schocher2015-04-01-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | move MACH_TYPE into defconfig Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | spl_atmel.c: Switch s_init to board_init_fTom Rini2015-04-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an empty stub of s_init(). It can be removed when lowlevel_init becomes s_init. Cc: Bo Shen <voice.shen@atmel.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini@ti.com> [rebased on current master, leave s_init() as empty stub] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: atmel: armv7: switch to use common timer functionsBo Shen2015-04-01-61/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8dfafdd (Introduce common timer functions), add common timer functions, we can use them directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: atmel: arm9: switch to use common timer functionsBo Shen2015-04-01-59/+18
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: at91: sama5d4: display the U-Boot version on LCDWu, Josh2015-04-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will display the U-Boot version on LCD. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* | | | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-03-31-462/+133
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| * | | | mtd: vf610_nfc: specify transfer size before each transferStefan Agner2015-03-30-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing showed, that commands like STATUS made the buffer dirty when executed with NFC_SECSZ set to the page size. It looks like the controller transfers bogus data when this register is configured. When setting it to 0, the buffer does not get altered while the status command still seems to work flawless. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | | mtd: vf610_nfc: mark page as dirty on block eraseStefan Agner2015-03-30-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver tries to re-use the page buffer by storing the page number of the current page in the buffer. The page is only read if the requested page number is not currently in the buffer. When a block is erased, the page number is marked as invalid if the erased page equals the one currently in the cache. However, since a erase block consists of multiple pages, also other page numbers could be affected. The commands to reproduce this issue (on a written page): > nand dump 0x800 > nand erase 0x0 0x20000 > nand dump 0x800 The second nand dump command returns the data from the buffer, while in fact the page is erased (0xff). Avoid the hassle to calculate whether the page is affected or not, but set the page buffer unconditionally to invalid instead. Signed-off-by: Stefan Agner <stefan@agner.ch>
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