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* Blackfin: serial: move early debug strings into .rodata sectionMike Frysinger2011-07-12-5/+5
| | | | | | | | | | Rewrite the assembly serial_early_puts() helper to place the strings in the .rodata section rather than embedding them directly in the .text section. Using .text is a little simpler, but it doesn't let people execute out of internal L1 sram (since core reads don't work on those regions). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: adi boards: also set stderr to nc with helperMike Frysinger2011-07-12-1/+2
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: update anomaly lists to latest public infoMike Frysinger2011-07-12-221/+335
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: serial: convert to bfin_{read,write} helpersMike Frysinger2011-07-12-17/+19
| | | | | | | | Since the serial struct declares the sizes for us, no need to hardcode them in the accessor functions. Let the bfin_{read,write} helpers do it for us. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: split out async setupMike Frysinger2011-07-12-50/+84
| | | | | | | | | | | We really only need to tweak the async banks in the initcode if the processor is booting out of it, otherwise we can wait until later on in the CPU booting setup. This also makes testing in the sim and early bring up over JTAG work much smoother when the initcode gets bypassed. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: adi boards: enable pretty flash progress outputMike Frysinger2011-07-12-0/+5
| | | | | | | | For only ~150 bytes increase in size, we can get a nice flash progress indicator rather than just the boring dots (which don't tell too much about overall progress). So enable it for all ADI boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: drop unused dma.h header from start codeMike Frysinger2011-07-12-1/+0
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: portmux: allow header to be included in assembly filesMike Frysinger2011-07-12-0/+4
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi supportHarald Krapfenbauer2011-07-12-3/+46
| | | | | | | | These boards have an mmc/sd slot on them connected over SPI, so enable the driver. Signed-off-by: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settingsHarald Krapfenbauer2011-07-12-47/+75
| | | | | | | | These boards can have an addon card plugged onto them, so enable support for it. Signed-off-by: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: sync MMR read/write helpers with LinuxMike Frysinger2011-07-12-46/+42
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: gpio: optimize free path a littleMike Frysinger2011-07-12-1/+4
| | | | | | | | | When we aren't doing resource tracking, the gpio_free() function is a stub that simply returns, so pull this logic up a level and make it an inline stub in the header. Now we don't have to waste time at any of the call sites. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDRMike Frysinger2011-07-12-1/+3
| | | | | | | Set the default post word location to an L1 data location for all Blackfin parts so things "just work" for most people. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: uart: fix printf warningMike Frysinger2011-07-12-1/+1
| | | | | | | The code uses %i to printf a size_t when it should use %zu, otherwise we get a warning from gcc about it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add init.elf helper codeMike Frysinger2011-07-12-2/+45
| | | | | | | | | This creates a standalone ELF that executes just the Blackfin initcode. This is useful for people who want to program the low level aspects of the CPU (memory/clocks/etc...) and can easily be used with JTAG for quick booting while developing. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: dont reset SWRST on newer bf526 partsMike Frysinger2011-07-12-1/+3
| | | | | | | The bug in the BF526 rom when doing a software reset exists only in older silicon versions, so don't clear SWRST on newer parts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: adi boards: enable multi serial support by defaultMike Frysinger2011-07-12-0/+4
| | | | | | Since this only adds less than 3KiB, enable for all ADI boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: uart: add multiple serial supportMike Frysinger2011-07-12-55/+222
| | | | | | | This brings CONFIG_SERIAL_MULTI support to the Blackfin on-chip UARTs. Ends up adding only ~512bytes per additional UART. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: uart: move debug buffers into local bssMike Frysinger2011-07-12-8/+3
| | | | | | | There's no need for these saved buffers to be global symbols, or in the data section. So mark them static to move them into the bss. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* powerpc/85xx: Add default usb mode and phy type to hwconfigRamneek Mehresh2011-07-11-4/+13
| | | | | | | | | | | Move to use hwconfig for usb mode & phy type instead of magic 'usb_phy_type' environment variable on the following platforms: MPC8536DS, P1020RDB, P1020RDB-PC, P1010RDB, P2020RDB, P2020RDB-PC, P2020RDB, P3041DS, P4080DS, & P5020DS. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/corenet_ds: add back buffer write for NOR flashYork Sun2011-07-11-0/+1
| | | | | | | | | Enable buffer write for better performance. This platform uses a NOR flash chip which supports write buffer programming. CFI driver can query the buffer size and use it to program the flash for best performance. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: remove SERDES4 soft-reset work-aroundTimur Tabi2011-07-11-22/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ed Swarthout <swarthou@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun2011-07-11-0/+6
| | | | | | | Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
* qoriq/p1_p2_rdb: USB device-tree fixups for P1020Ramneek Mehresh2011-07-11-0/+47
| | | | | | | | | | Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Specify hwconfig usage for USB controllerRamneek Mehresh2011-07-11-0/+25
| | | | | | | Specify hwconfig usage for USB mode and phy change Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Update USB mode device tree fixupRamneek Mehresh2011-07-11-12/+65
| | | | | | | | | | | | Modify support for USB mode fixup: - Add common support for USB mode and phy type device tree fix-up for all USB controllers mentioned in hwconfig string - Fetch USB mode and phy type via hwconfig; if not defined in hwconfig, then fetch them from env Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add basic support for P1023RDS boardRoy Zang2011-07-11-0/+1303
| | | | | | | | | | | | | | The P1023RDS board is the reference board for the P1023 SoC. Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, UART, I2C, etc. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xx: Display a warning for unsupported DDR data ratesYork Sun2011-07-11-4/+27
| | | | | | | | If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/corenet_ds: Fix RCW overriding for RDIMMYork Sun2011-07-11-1/+1
| | | | | | | Allow overriding RCW for all RDIMM, not only quad-rank ones. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: fix DDR data width checkingYork Sun2011-07-11-8/+27
| | | | | | | | | Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Adding fallback to raw timing on supported boardsYork Sun2011-07-11-0/+8
| | | | | | | | In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Enable calculation for fixed DDR chipsYork Sun2011-07-11-3/+39
| | | | | | | | | | We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix pin muxing for second USB controllerFelix Radensky2011-07-11-1/+1
| | | | | | | | | | | On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Adding more SPD registersYork Sun2011-07-11-1/+3
| | | | | | | Adding byte 32 and 33 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add 16-bit support for DDR3York Sun2011-07-11-2/+18
| | | | | | | | Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: check SPD length before using part numberYork Sun2011-07-11-1/+2
| | | | | | | | Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram widthYork Sun2011-07-11-4/+20
| | | | | | | | If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: display boot device and bank on the MPC8610 HPCDTimur Tabi2011-07-11-2/+23
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add NAND boot support for P3041/P5020DSShaohui Xie2011-07-11-6/+25
| | | | | | | When booting from NAND we get the environment and FMan ucode from NAND. Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add P2041 processor supportKumar Gala2011-07-11-0/+26
| | | | | | The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2040: Add various p2040 specific informationMingkai Hu2011-07-11-0/+133
| | | | | | | | | | | Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't setKumar Gala2011-07-11-13/+24
| | | | | | | | | | | Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* qoriq/p1_p2_rdb: Add Dual Role USB support macro for P1020RDBRamneek Mehresh2011-07-11-0/+1
| | | | | | | Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't setKumar Gala2011-07-11-0/+2
| | | | | | | | Add ifdef protection in LBC code to handle the case in which CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't setKumar Gala2011-07-11-0/+8
| | | | | | | | Add ifdef protection in LAW & TLB code to handle the case in which CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC83XX: Fix PCI express clock setupBill Cook2011-07-06-2/+4
| | | | | | | | | | | | On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook@isgchips.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/83xx: remove empty board_early_init_f()Timur Tabi2011-07-06-13/+0
| | | | | | | Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add support for MergerBox boardAndre Schwarz2011-07-06-0/+1504
| | | | | | | | Includes board config file, documentation, maintainer and boards.cfg entries, and board specific files in vendor dir. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC83xx: add config options for memory setup.Andre Schwarz2011-07-06-1/+18
| | | | | | | | | CPO value and driver strength settings are board specifc. Also allow SPD data fetch from any accessible I2C EEPROM. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC83xx: add define for global half-strength enable (HSE)Andre Schwarz2011-07-06-0/+1
| | | | | Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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