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* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-07-24-0/+62
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| * Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2010-07-24-0/+62
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| | * i2c: soft_i2c: add simple GPIO implementationMike Frysinger2010-07-22-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the vast majority of GPIO I2C implementations behave the same way, support the common GPIO framework with default settings. This adds two new defines CONFIG_SOFT_I2C_GPIO_{SCL,SDA} so that boards which want GPIO I2C support need only define these. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-07-24-451/+1129
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| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-24-33/+440
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| | * | ppc4xx: Enable "ecctest" command on t3corpStefan Roese2010-07-23-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Enable "ecctest" command on katmaiStefan Roese2010-07-23-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 coreStefan Roese2010-07-23-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add "ecctest" command to test/simulate ECC errorsStefan Roese2010-07-23-0/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: DDR/ECC: Use correct macros to clear error statusStefan Roese2010-07-23-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Only define DDR2 registers for the correct PowerPC variantsStefan Roese2010-07-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC valuesStefan Roese2010-07-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: T3CORP fixes and updatesStefan Roese2010-07-23-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 .................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx/Canyonlands added USB board callbacksRupjyoti Sarmah2010-07-23-9/+63
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | powerpc/85xx: Rework P1022 SERDES is_serdes_configured supportKumar Gala2010-07-21-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured supportKumar Gala2010-07-21-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p3041: Add various p3041 related definesKumar Gala2010-07-20-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p3041 to cpu_type_list and SVR list * Added number of LAWs for p3041 * Set CONFIG_MAX_CPUS to 4 for p3041 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p5020: Add various p5020 related defines (and p5010)Kumar Gala2010-07-20-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p5020 & p5010 to cpu_type_list and SVR list * Added number of LAWs for p5020 * Set CONFIG_MAX_CPUS to 2 for p5020 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc85xx: Report FMAN # to match user manualEmil Medve2010-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | The user manual refers to FMAN1 and FMAN2 not 0 and 1. Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p4080: Add setting of clock-frequency for clockgen nodeKumar Gala2010-07-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | On QorIQ CoreNet based devices we have a global clocking block. We want to keep track of SYSCLK frequency as it is what is used to derive all other frequencies in the SoC Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updatesKumar Gala2010-07-20-8/+11
| | | | | | | | | | | | | | | | | | | | | Move to using fdt_node_offset_by_compat_reg to find the node offsets we want to update instead of using aliases. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-162/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fdt: Add fdt_node_offset_by_compat_reg helperKumar Gala2010-07-20-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a compatible string and physical address try and find a node that matches. This is useful when we want to find a specific device node to update (for example if we have multiple PCI nodes we can use the physical address to distinguish them when trying to update the device tree). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | fdt: Add fdt_translate_address to convert reg node to cpu phys addrKumar Gala2010-07-20-0/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is extracted out of the Linux Kernel code from arch/powerpc/kernel/prom_parse.c. We maintain some of the same structure to support multiple bus types even though we only have one in the current code. In the future we might want to translate across a PCI bus and thus it will be easier to add that functionality back in. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641Kumar Gala2010-07-20-138/+136
| | | | | | | | | | | | | | | | | | | | | | | | The MPC8641 boards actually only have PCIE not PCI. Rename so we are uniform with regards to names so we can replace this code with templated code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.hKumar Gala2010-07-20-16/+21
| | | | | | | | | | | | | | | | | | | | | | | | Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on MPC8641 boards since its really PCIE controllers and not PCI. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.hKumar Gala2010-07-20-49/+20
| |/ | | | | | | | | | | | | Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of /home/wd/git/u-boot/master/Wolfgang Denk2010-07-21-0/+0
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| * Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2010-07-17-4/+4
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* | \ Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2010-07-17-4/+4
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| * video: cleanup comments in cfb_console.c and video_fb.hAnatolij Gustschin2010-07-17-4/+4
| | | | | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Drop support for GTH boardWolfgang Denk2010-07-17-2432/+2
|/ | | | | | | | | | | | | | | The board maintainer states: The GTH board is obsolete and has not been manufactured for several years. To my knowledge, no recent U-Boot build has been tested on that card. So drop support for this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Acked-by: Thomas Lange<thomas@corelatus.se>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-07-16-1355/+2370
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| * powerpc/85xx: Move p1022ds slot code into board fileKumar Gala2010-07-16-70/+69
| | | | | | | | | | | | | | | | The code to map SERDES configs to slot names is board specific and not chip specific. Thus it should live in board/freescale/p1022ds/ and not in arch/powerpc/cpu/. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Convert MPC8536DS to using board common ICS307 codeKumar Gala2010-07-16-157/+6
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Convert MPC8572DS to using board common ICS307 codeKumar Gala2010-07-16-153/+7
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add command to report errata workaroundsKumar Gala2010-07-16-3/+55
| | | | | | | | | | | | | | | | | | Add 'errata' command to report what errata we workaround. Report workaround for erratum SATA-A001 on P1022/P1013. Also sorted the CONFIG_CMD_* list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc: add support for the Freescale P1022DS reference boardTimur Tabi2010-07-16-0/+1184
| | | | | | | | | | | | | | | | | | | | | | | | | | Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx/p1_p2_rdb: PCIe E1000 card support added.Poonam Aggrwal2010-07-16-0/+1
| | | | | | | | | | | | | | | | Enables the Intel Pro/1000 PT Gb Ethernet PCI-E Network Adapter configuration support for P1/P2 RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl: add LAW target to fsl_pci_info structureTimur Tabi2010-07-16-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for link stack & STAC on e5500Kumar Gala2010-07-16-1/+3
| | | | | | | | | | | | | | | | The e5500 has a link register stack and segment target address cache. Its safe to enable these bits on older e500 cores as the bits are implemented in the register. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add recognition of e5500 coreKumar Gala2010-07-16-10/+18
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc 83xx/85xx: Merge lbc upmconfig codeBecky Bruce2010-07-16-127/+53
| | | | | | | | | | | | | | | | | | | | Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Add reginfo commandBecky Bruce2010-07-16-0/+41
| | | | | | | | | | | | | | | | The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_law.c: Add print_laws() for FSL_CORENET platforms.Becky Bruce2010-07-16-0/+6
| | | | | | | | | | | | | | Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms. Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * drivers/misc/fsl_law.c: Rearrange code to avoid duplicationBecky Bruce2010-07-16-77/+49
| | | | | | | | | | | | | | | | The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Add print_tlbcam() functionBecky Bruce2010-07-16-0/+21
| | | | | | | | | | | | | | This dumps out the contents of TLB1 on 85xx-based systems. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: tlb.c cleanupsBecky Bruce2010-07-16-26/+25
| | | | | | | | | | | | | | | | | | | | | | Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-500/+318
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc: Update configs to properly set FSL_ELBCBecky Bruce2010-07-16-0/+6
| | | | | | | | | | | | | | | | | | | | | | Some parts that have an Enhanced Local Bus Controller weren't setting CONFIG_FSL_ELBC. Fix this so we can use this define properly going forward (currently it's only used if PHYS_64BIT is set, which meant not all platforms needed to have it set correctly). Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-02 06:01:34 +0000