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* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-03-15-121/+493
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| * sh: ap325rxa: Change the wait cycle in the area 5Yusuke.Goda2009-03-13-1/+1
| | | | | | | | | | Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Fix cannot work rtl8139 on r2dplusYoshihiro Shimoda2009-03-12-0/+3
| | | | | | | | | | | | | | | | The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory registration. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add netdev header fixing of warning/buildNobuhiro Iwamatsu2009-03-12-0/+1
| | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add support 32-Bit Extended Address Mode to sh7785lcrYoshihiro Shimoda2009-03-12-4/+399
| | | | | | | | | | | | | | | | We can built 'make sh7785lcr_32bit_config'. And add new command "pmb" for this mode. This command changes PMB for using 512MB system memory. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add some register value configurable to PCI of SH7780Yoshihiro Shimoda2009-03-12-3/+9
| | | | | | | | | | | | | | | | Some register value was hardcoded for System memory size 128MB and memory offset 0x08000000. This patch fixed the problem. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add system memory registration to PCI for SH4Yoshihiro Shimoda2009-03-12-0/+10
| | | | | | | | | | | | | | It is necessary for some pci device driver. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add value for PCI system memory registration of sh7785lcrYoshihiro Shimoda2009-03-12-0/+4
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add macros for SH-4A 32-Bit Address Extended ModeYoshihiro Shimoda2009-03-12-0/+25
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: use write{8,16,32} in ms7720se lowlevel_initNobuhiro Iwamatsu2009-03-12-114/+42
| | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-03-15-7/+11
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| * | mpc83xx: Add bank configuration to FSL spd_sdram.cJerry Van Baren2009-03-14-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: correctly set encryption and I2C bus 0 clockNorbert van Bolhuis2009-03-14-1/+1
| |/ | | | | | | | | | | | | | | | | | | This patch makes sure the correct mask is applied when setting the encryption and I2C bus 0 clock in SCCR. Failing to do so may lead to ENCCM being 0 in which case I2C bus 0 won't function. Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-03-15-0/+50
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| * | OMAP3: Add support for OMAP3 die IDDirk Behme2009-03-13-0/+50
| |/ | | | | | | | | | | Read and store OMAP3 die ID in U-Boot environment. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-pxaWolfgang Denk2009-03-15-22/+24
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| * | PXA: timer use do_div and simplify itJean-Christophe PLAGNIOL-VILLARD2009-03-09-22/+24
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | | MPC5200 FEC MII speed registerJon Smirl2009-03-13-7/+16
| |/ |/| | | | | | | | | Set a non-zero speed in the MII register so that MII commands will work. Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-03-10-10/+6
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| * | tsec: report when there is no vendor specific PHY supportPaul Gortmaker2009-03-09-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit af1c2b84 added a generic phy support, with an ID of zero and a 32 bit mask; meaning that it will match on any PHY ID. The problem is that there is a test that checked if a matching PHY was found, and if not, it printed the non-matching ID. But since there will always be a match (on the generic PHY, worst case), this test will never trip. In the case of a misconfigured PHY address, or of a PHY that isn't explicitly supported outside of the generic support, you will never see the ID of 0xffffffff, or the ID of the real (but unsupported) chip. It will silently fall through onto the generic support. This change makes that test useful again, and ensures that the selection of generic PHY support doesn't happen without some sort of notice. It also makes it explicitly clear that the generic PHY must be last in the PHY table. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * | Add eTSEC 1/2 IO override control (corrected)ksi@koi8.net2009-03-09-1/+1
| | | | | | | | | | | | | | | | | | This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
| * | fsl: Remove unnecessary debug printfsAndy Fleming2009-03-09-3/+0
| | | | | | | | | | | | | | | | | | | | | These were left in accidentally, and are not really useful unless the code is as broken as it was when it was being developed. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Fix mpc85xx ddr-gen3 ddr_sdram_cfg.Ed Swarthout2009-03-09-2/+2
| |/ | | | | | | | | | | | | Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-03-10-0/+0
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| * | SIMPC8313 board: fix out of tree building.Wolfgang Denk2009-03-09-9/+18
| |/ | | | | | | | | | | | | | | | | | | Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | SIMPC8313 board: fix out of tree building.Wolfgang Denk2009-03-09-9/+18
|/ | | | | | | | | Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-03-09-70/+259
|\ | | | | | | | | | | | | Conflicts: lib_ppc/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * 8360, kmeter1: added bootcount feature.Heiko Schocher2009-03-05-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU. The bootcounter uses 8 bytes from the muram, because no other memory was found on this CPU for the bootcount feature. So we must correct the muram size in DTS before booting Linux. This feature is actual only implemented for MPC8360, because not all 83xx CPU have qe, and therefore no muram, which this feature uses. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx, kmeter: QE_ENET10 errata for Silicon Revision 2.1Heiko Schocher2009-03-05-8/+12
| | | | | | | | | | | | | | | | | | | | old code implemented the QE_ENET10 errata only for Silicon Revision 2.0. New code reads now the Silicon Revision register and sets dependend on the Silicon Revision the values as advised in the QE_ENET10 errata. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx, kmeter1: updates for 2009.03Heiko Schocher2009-03-05-31/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - HRCW update HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL HRCWH_LALE_EARLY added - DDR-SDRAM settings modified. This solves sporadically problems with this memory. - CS1 now 128 MB window size - CS3 now 512 MB window size - PRAM activated - MTDPARTS_DEFAULT defined - CONFIG_HOSTNAME added - MONITOR_LEN now 384 KB Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx, kmeter1: autodetect size of DDR II RAMHeiko Schocher2009-03-05-12/+20
| | | | | | | | | | | | | | | | it is possible that some board variants have different DDR II RAM sizes. So we autodetect the size of the assembled RAM. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx, i2c: add mux support for fsl_i2cHeiko Schocher2009-03-05-1/+21
| | | | | | | | | | | | | | | | | | | | This patch adds I2C mux support for the fsl_i2c driver. This allows you to add "new" i2c busses, which are reached over i2c muxes. For more infos, please look in the README and search for CONFIG_I2C_MUX. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx, kmeter1: add I2C, dtt, eeprom supportHeiko Schocher2009-03-05-8/+69
| | | | | | | | | | | | | | | | | | | | This patch adds I2C support for the Keymile kmeter1 board. It uses the First I2C Controller from the CPU, for accessing 4 temperature sensors, an eeprom with IVM data and the booteeprom over a pca9547 mux. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * i2c, dtt: move dtt_init () to board_init_r ()Heiko Schocher2009-03-05-1/+4
| | | | | | | | | | | | | | | | In case where a board not uses CONFIG_POST, it is not necessary to init the DTTs when running from flash. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx: Fix some bugs in spd sdram codeDave Liu2009-03-05-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * MPC8349ITX: several config issues fixedValeriy Glushkov2009-03-05-0/+5
| | | | | | | | | | | | | | | | | | The previous version rebooted forever with DDR bigger than 256MB. Access the DS1339 RTC chip is on I2C1 bus. Allow DHCP. Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signalAnton Vorontsov2009-03-05-7/+7
| | | | | | | | | | | | | | | | | | | | The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | i2c, dtt: move dtt_init () to board_init_r ()Heiko Schocher2009-03-02-3/+3
| | | | | | | | | | | | | | it is not necessary to init the DTTs so early, so move this init to board_init_r (). Signed-off-by: Heiko Schocher <hs@denx.de>
* | lcd: Fix compilation warning in common/lcd.cAnatolij Gustschin2009-02-25-1/+4
| | | | | | | | | | | | | | | | | | Fix following warning while compilation for mcc200 board: lcd.c: In function 'lcd_display_bitmap': lcd.c:625: warning: unused variable 'cmap' Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Moved SC520 Files (fix commit 407976185e0dda2c90e89027121a1071b9c77bfb)Graeme Russ2009-02-25-5/+53
| | | | | | | | | | | | Fixes commit 407976185e0dda2c90e89027121a1071b9c77bfb Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
* | smc911x: split out useful defines/functions into local headerMike Frysinger2009-02-25-455/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The smc911x driver has a lot of useful defines/functions which can be used by pieces of code (such as example eeprom programmers). Rather than forcing each place to duplicate these defines/functions, split them out of the smdc911x driver into a local header. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Guennadi Liakhovetski <lg@denx.de> CC: Magnus Lilja <lilja.magnus@gmail.com> CC: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2009-02-24-58/+1325
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| * | ARM: add an "eet" variant of the imx31_phycore boardGuennadi Liakhovetski2009-02-24-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "eet" variant of the imx31_phycore board has an OLED display, using a s6e63d6 display controller on the first SPI interface, using GPIO57 as a chip-select for it. With this configuration you can display 256 colour BMP images in 16-bit RGB (RGB565) LCD mode. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | video: add an i.MX31 framebuffer driverGuennadi Liakhovetski2009-02-24-0/+857
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Synchronous Display Controller and the Display Interface on i.MX31, using IPU for DMA channel setup. So far only displaying of bitmaps is supported, no text output. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | LCD: support 8bpp BMPs on 16bpp displaysGuennadi Liakhovetski2009-02-24-33/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also simplifies some ifdefs in lcd.c, introduces a generic vidinfo_t, which new drivers are encouraged to use and old drivers to switch over to. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | Add 16bpp BMP supportMark Jackson2009-02-24-10/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 16bpp BMP support to the common lcd code. Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code. At the moment it's only been tested on the MIMC200 AVR32 board, but extending this to other platforms should be a simple task !! Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | A driver for the S6E63D6 SPI display controller from SamsungGuennadi Liakhovetski2009-02-24-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the S6E63D6 SPI OLED display controller from Samsung. It only provides access to controller's registers so the client can freely configure it. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | i.MX31: support GPIO as a chip-select in the mxc_spi driverGuennadi Liakhovetski2009-02-24-8/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPI devices have special requirements on chip-select handling. With this patch we can use a GPIO as a chip-select and strictly follow the SPI_XFER_BEGIN and SPI_XFER_END flags. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | i.MX31: add a simple gpio driverGuennadi Liakhovetski2009-02-24-1/+95
| | | | | | | | | | | | | | | | | | | | | | | | This is a minimal driver, so far only managing output. It will be used by the mxc_spi.c driver. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | i.MX31: fix SPI driver for shorter than 32 bitGuennadi Liakhovetski2009-02-24-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | Fix setting the SPI Control register, 8 and 16-bit transfers and a wrong pointer in the free routine in the mxc_spi driver. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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