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* powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-551/+69
| | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-150/+9
| | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Remove config.mk for nand linker scriptKumar Gala2011-04-04-121/+4
| | | | | | | Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala2011-04-04-93/+10
| | | | | | | | We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update P2020DS default env settingsLi Yang2011-04-04-10/+12
| | | | | | | | | | | | | | Read MAC address from EEPROM. Add hwconfig settings. Modified the default othbootargs to include the cache-sram-size parameter. This parameter is needed as the L2 as SRAM is ON by default in the P2020RDB kernel and used by the Gianfar driver. Also cleanup some of the boot commands. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add eSDHC support on P2020DSJerry Huang2011-04-04-1/+37
| | | | | | | | | | | We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020Kumar Gala2011-04-04-0/+15
| | | | | | | Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"Pankaj Chauhan2011-04-04-0/+3
| | | | | | | | | In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala2011-04-04-6/+2
| | | | | | | | | Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr initKumar Gala2011-04-04-35/+28
| | | | | | | | | | Rather than having #defines DATARATE_*_MHZ, lets just match what we do on the SPD code and convert the DDR frequency into MHZ and just compare with a constant. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* p1022ds: allow for board-specific ngPIXIS functionsTimur Tabi2011-04-04-18/+112
| | | | | | | | | | | | | | | | The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC SOCs. Although programming the ngPIXIS is mostly standard on all boards that have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in "indirect" mode whenever the video display (DIU) is active. To support indirect mode, and to make it easier to support other quirks on future reference boards, the low-level ngPIXIS functions are all marked as weak, so that board-specific code can override any of them. We take advantage of this feature on the P1022DS, so that we can properly reset the board when the DIU is active. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for Integrated Flash Controller (IFC)Dipen Dudhat2011-04-04-2/+1056
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add SERDES support for P1010/P1014Prabhakar Kushwaha2011-04-04-0/+82
| | | | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PINmichael2011-04-01-0/+2
| | | | | | | | | | | | If NCE is hooked up to NCS3, we don't need to (and can't) explicitly set the state of the NCE pin. Instead, the controller asserts it automatically as part of a command/data access. Only "CE don't care"-type NAND chips can be used in this manner. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
* NAND: add support for reading ONFI page tableFlorian Fainelli2011-04-01-49/+213
| | | | | | | | | | | | This patch adds support for reading an ONFI page parameter from a NAND device supporting it. If this is the case, struct nand_chip onfi_version member contains the supported ONFI version, 0 otherwise. This allows NAND drivers past nand_scan_ident to set the best timings for the NAND chip. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Fix NAND_SPL and ONENAND_IPL in MakefileHaiying Wang2011-04-01-16/+14
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: add more watchdog resetsScott Wood2011-04-01-0/+8
| | | | | | | Poke the watchdog in a variety of looping constructs, which could take a long time to complete. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Prepare v2011.03v2011.03Wolfgang Denk2011-03-31-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix build issues cause by LDFLAGS_FINAL changesWolfgang Denk2011-03-31-48/+48
| | | | | | | | | | | Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a number of Makefiles in a way that broke out-of-tree builds. The problem was that $(nandobj) was used before it got defined. Fix this. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-03-31-1/+67
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| * powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-1/+60
| | | | | | | | | | | | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang2011-03-28-0/+7
| | | | | | | | | | | | | | | | | | | | Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2011-03-31-0/+5
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| * | cfi_flash: fix bug with flash banks with different sector numbersMartin Krause2011-03-28-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function find_sector() does not take into account if the flash bank has changed since the last call. This could lead to illegal accesses inside and beyond the flash_info_t info strcture. For example if the current flash bank has less sectors than the last used flash bank. This patch adds two cheks. One that insures, that the current sector does not exceed the allowed maximum (which is always a good idea). And one that checks if the current access is to the same flash bank as the last access. If not, the search loop will start with sector 0. Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Fix build problems caused by "_end" -> "__bss_end__" renameWolfgang Denk2011-03-31-4/+4
|/ | | | | | | | | | | | | | | | Commit 44c6e65 "rename _end to __bss_end__ broke building of a large number of systems (at least all PowerPC?): libstubs.o: In function `app_startup': examples/standalone/stubs.c:197: undefined reference to `__bss_end__' The rename should not be done for the files in the examples/standalone/ directory, as these are not using the code from start.S, but do their own BSS clearing, and either use their own linker scripts or the ones provided by the compilers. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Prepare vv2011.03-rc2Wolfgang Denk2011-03-27-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2011-03-27-11/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-329/+680
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| * arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h updateTom Warren2011-03-27-1/+1
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * S5P: mmc: Resolved interrupt error during mmc_initChander Kashyap2011-03-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Blocksize was hardcoded to 512 bytes. But the blocksize varies depeding on various mmc subsystem commands (between 8 and 512). This hardcoding was resulting in interrupt error during data transfer. It is now calculated based upon the request sent by mmc subsystem. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARMV7: S5P: Fixed register offset in mmc.hChander Kashyap2011-03-27-4/+6
| | | | | | | | | | | | | | | | | | | | | | The MMC registers are accessed through struct s5p_mmc member variables. MMC controller "control4" register offset is set to 0x8C as per data sheet. The size of struct s5p_mmc is also corrected. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * S5P: timer: replace bss variable by gdMinkyu Kang2011-03-27-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | Use the global data instead of bss variable, replace as follow. count_value -> removed timestamp -> tbl lastdec -> lastinc Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
| * S5P: universal: Enable the pwm driverMinkyu Kang2011-03-27-0/+3
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * S5P: goni: Enable the pwm driverMinkyu Kang2011-03-27-0/+3
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * S5P: smdkc100: Enable the pwm driverMinkyu Kang2011-03-27-0/+3
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * S5P: timer: Use pwm functionsMinkyu Kang2011-03-27-58/+7
| | | | | | | | | | | | Use pwm functions for timer that is PWM timer 4. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: S5P: pwm driver supportDonghwa Lee2011-03-27-0/+259
| | | | | | | | | | | | | | | | This is common pwm driver of S5P. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fixup dram_init for relocation supportseedshope2011-03-27-1/+7
| | | | | | | | | | Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Disable LED function in start.s on the nand bootingseedshope2011-03-27-0/+2
| | | | | | | | | | | | | | | | | | | | Since nand boot have some limit for the first 4KB, We only disable the LED function to reduce the code space. At the same time, Fix the compile error for LED function undefined in the compile time of nand_spl. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Add some labels to u-boot.lds to support nand_splseedshope2011-03-27-1/+16
| | | | | | | | | | | | | | | | In the nand_spl feature of SMDK6400. Add some relocation symbols to nand_spl/board/samsung/smdk6400/u-boot.lds to fix the compile error. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fix the mutiple link errorseedshope2011-03-27-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The first, the cpu_init.o have already been link for cmd_link_o_target atfer compile, But, The link script re-link the point file. So the link machine will generate multiple definition error information. The second, Since the first 4kB of nand boot featue code move to nand_spl, So It is not necessary to force the cpu_init.o in non-nand boot. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fix some label undefined in build errorseedshope2011-03-27-3/+24
| | | | | | | | | | | | | | | | | | | | Modify Makefile for cpu_init.c and Start.s use some label,this defined u-boot.lds of arch/arm/cpu/arm1176. But SMDK6400 use the link script board/samsung/smdk6400/u-boot-nand.lds. So add some label form u-boot.lds to u-boot-nand.lds Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefinedseedshope2011-03-27-0/+5
| | | | | | | | | | | | | | Fix CONFIG_SYS_INIT_SP_ADDR undefined issue. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: fix incorrect monitor protection region in FLASHPo-Yu Chuang2011-03-27-1/+88
| | | | | | | | | | | | | | | | | | | | | | Monitor protection region in FLASH did not cover .rel.dyn and .dynsym sections, because it uses __bss_start to compute monitor_flash_len. Use _end instead. Add _end to linker scripts for end of u-boot image Add _end_ofs to all the start.S. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
| * rename _end to __bss_end__Po-Yu Chuang2011-03-27-263/+263
| | | | | | | | | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* | powerpc/85xx: Fix PCI memory map setup on P1_P2_RDBPrabhakar Kushwaha2011-03-24-14/+14
| | | | | | | | | | | | | | | | | | Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134York Sun2011-03-24-0/+41
| | | | | | | | | | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun2011-03-24-0/+2
| | | | | | | | | | | | | | | | rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMsYork Sun2011-03-24-32/+78
| | | | | | | | | | | | | | | | Tested all possible values for clk_adjust and write_data_delay for dual rank UDIMM and RDIMM to revise the tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun2011-03-24-1/+6
|/ | | | | | | | To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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