summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* cmd_nand: Remove duplicate includePeter Tyser2009-11-13-8/+0
| | | | | | Also remove vague, unnecessary comment Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Katmai: Add chip_config commandStefan Roese2009-11-10-220/+66
| | | | | | | This patch removes the Katmai "bootstrap" command and replaces it with the now common command "chip_config". Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Switch to I2C bus numer 0 for chip_config commandStefan Roese2009-11-10-0/+6
| | | | | | | | | All currently available 4xx derivats have the I2C bootstrap EEPROM located on I2C bus number 0. This patch now first sets this bus number, so that the chip_config command also works for board with multiple I2C busses, like Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add UBI support to PLU405 boardsMatthias Fuchs2009-11-10-4/+14
| | | | | | | | | -add UBI support -increase malloc'able memory size -cleanup MONITOR|FLASH_BASE|LEN constants Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix NAND booting targets after 4xx linker script consolidationStefan Roese2009-11-09-0/+20
| | | | | | | Somehow I missed the NAND booting targets in the 4xx linker script consolidation patchset. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove duplicated is_pci_host() functionsStefan Roese2009-11-09-387/+25
| | | | | | | | | This patch introduces a weak default function for is_pci_host(), returning 1. This is the default behaviour, since most boards only implement PCI host functionality. This weak default can be overridden by a board specific version if needed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-442/+172
| | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove board specific linker scripts from most PPC4xx boardsStefan Roese2009-11-02-9566/+0
| | | | | | | | | All these linker scripts can be removed since the new common ppc4xx linker script should be able to handle all of those boards. Please test and report problems. Thanks. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add common ppc4xx linker scriptStefan Roese2009-11-02-0/+172
| | | | | | | | This linker script can be used by all PPC4xx platforms. It works for PPC405 and PPC440 platforms. Boards which need a board specific linker script can override this default linker script in board/*/config.mk. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add custom linker script to board/*/config.mkStefan Roese2009-11-02-0/+12
| | | | | | | | These boards have special linker scripts right now. We can't use the common 4xx linker script here. So overrride the linker script (LDSCRIPT) in board/*/config.mk and choose the board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problems in some ppc4xx board MakefilesStefan Roese2009-11-02-5/+5
| | | | | | | | | | Some 4xx Makefiles didn't add $(SOBJ) to their board library. This was no till now problem, since those boards included this object (init.o most of the time) directly from their linker scripts. This patch clean this up, so that all objects are now collected in the board library. This is in preparation for the upcoming PPC4xx linker script consolidation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: sc3: Remove unreferenced external declarations from sc3.hStefan Roese2009-11-02-5/+0
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mkconfig: Create board directory (CONFIG_BOARDDIR) in include/config.hStefan Roese2009-11-02-0/+9
| | | | | | | | | | | | | This patch extends the mkconfig script to automatically create a define for the board directory in include/config.h: #define CONFIG_BOARDDIR board/amcc/canyonlands This is needed for the upcoming PPC4xx linker script consolidation, where the PPC440 platforms need to include a board specific file in the common linker script. Signed-off-by: Stefan Roese <sr@denx.de>
* mpc52xx: add support for the IPEK01 boardWolfgang Grandegger2009-10-31-0/+776
| | | | | | | This patch adds support for the board IPEK01 based on the MPC5200. The Futjitsu Lime graphics controller is configured in 16 bpp mode. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* Merge branch 'next' of git://git.denx.de/u-boot-video into nextWolfgang Denk2009-10-31-55/+76
|\
| * video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01Wolfgang Grandegger2009-10-31-1/+3
| | | | | | | | | | | | | | | | | | | | In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words for D32 accesses due to the diffferent connecting to the GDC bus. This patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP, which should be set for all board using the mb862xx in 16 bpp mode. For the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp modeAnatolij Gustschin2009-10-31-1/+19
| | | | | | | | | | | | | | | | | | | | | | The new IPEK01 board can use the 32 bpp mode for the Lime graphics controller. For this mode, video accelaration does not work. This patch makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL, which is enabled for the lwmon5 and the socrates board for backward compatibility. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * video: mb862xx: improve board-specific Lime configurationWolfgang Grandegger2009-10-31-53/+54
| | | | | | | | | | | | | | | | | | | | | | To avoid board-specific code accessing the mb862xx registers directly, the public function mb862xx_probe() has been introduced. Furthermore, the "Change of Clock Frequency" and "Set Memory I/F Mode" registers are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR, respectively. The BSPs for the socrates and lwmon5 boards have been adapted accordingly. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* | new PCA9564 i2c bridge driverValentin Yakovenkov2009-10-30-0/+240
| | | | | | | | | | Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: TWI/I2C: implement bus speed get/set functionsMike Frysinger2009-10-30-11/+48
| | | | | | | | | | | | While we're here, improve the speed calculation a bit to match the HRM. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: TWI/I2C: add timeout to transferMike Frysinger2009-10-30-3/+12
|/ | | | | | | The current transfer code relies on ctrlc() to abort transfers, but this requires user interactivity. Naturalize the process with a timeout. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-10-28-133/+175
|\
| * cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-133/+175
| | | | | | | | | | | | | | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sparcWolfgang Denk2009-10-28-2/+2
|\ \
| * | Fix bug in jumptable call stubs for SPARC.Sergey Mironov2009-10-27-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Sergey Mironov <ierton@gmail.com> Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* | | Fix Compliation warning for TNY-A9260 and TNY-A9G20Sandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Fix Compliation warning for SBC35-A9G20 boardSandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | galaxy5200: Add default environment variablesEric Millbrandt2009-10-28-2/+8
| |/ |/| | | | | | | | | | | Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* | Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-56/+6210
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Add 'editenv' commandPeter Tyser2009-10-27-0/+43
| | | | | | | | | | | | | | | | | | The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | setenv(): Delete 0-length environment variablesPeter Tyser2009-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Previously setenv() would only delete an environment variable if it was passed a NULL string pointer as a value. It should also delete an environment variable when it encounters a valid string pointer of 0-length. This change/fix is generally useful and is necessary for the upcoming "editenv" command. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | readline(): Add ability to modify a string bufferPeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | If the 'buf' parameter is a non-0-length string, its contents will be edited. Previously, the initial contents of 'buf' were ignored and the user entered its contents from scratch. This change is necessary to support the upcoming "editenv" command but could also be used for future commands which require a user to modify an existing string. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | cread_line(): Remove unused variablesPeter Tyser2009-10-27-4/+1
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Check for NULL prompt in readline_into_buffer()Peter Tyser2009-10-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, passing readline() or readline_into_buffer() a NULL 'prompt' parameter would result in puts() printing garbage when CONFIG_CMDLINE_EDITING was enabled. Note that no board currently triggers this bug. Enabling CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in the bug appearing. This change is only intended to prevent someone from running into this issue in the future. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | drivers/net/phy/miiphybb.c: fix warning: no newline at end of fileWolfgang Denk2009-10-27-1/+1
| | | | | | | | | | | | | | | | Add missing newline. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com> Cc: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-10-27-81/+460
|\ \
| * | mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | xpedite5370: Enable multi-core supportPeter Tyser2009-10-27-4/+17
| | | | | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal2009-10-27-8/+8
| | | | | | | | | | | | | | | | | | | | | The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fdt_support: Add multi-serial support for stdout fixupAnton Vorontsov2009-10-26-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX constant. With multi-serial support, the CONS_INDEX may no longer represent actual console, so we should try to extract port number from the current stdio device name instead of always hard-coding the constant value. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
| | | | | | | | | | | | | | | | | | | | | According the user manual, we need loop-check the L2 enable bit set. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-25 22:35:34 +0000