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* mpc83xx: MPC8360E-RDK: rework ddr setup, enable eccAnton Vorontsov2008-03-25-13/+38
| | | | | | | | Current DDR setup easily causes memory corruption, this patch fixes it. Also fix TIMING_CFG0_MRS_CYC definition. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCIAnton Vorontsov2008-03-25-0/+17
| | | | | | | This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen controller and FHCI (QE USB). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc83xx: MPC8360E-RDK: add support for NANDAnton Vorontsov2008-03-25-1/+99
| | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc83xx: MPC8360E-RDK: use RGMII_RXID interface modeAnton Vorontsov2008-03-25-2/+2
| | | | | | This is needed for BCM PHYs to work on this board. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* uec: add support for Broadcom BCM5481 Gigabit PHYAnton Vorontsov2008-03-25-0/+41
| | | | | | | | | This patch adds basic support for Broadcom BCM5481 PHY. RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is Peter Barada <peterb@logicpd.com>. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* uec: add support for RGMII_RXID interface modeAnton Vorontsov2008-03-25-0/+2
| | | | | | | PHY drivers will use it to setup software delay between RXD and RXC signals. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* uec: add support for gbit mii status readingsAnton Vorontsov2008-03-25-9/+24
| | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boardsAnton Vorontsov2008-03-25-0/+1
| | | | | | This is primarily for the early console support. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: initialize serdes for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+43
| | | | | | | | On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: serdes setup routinesAnton Vorontsov2008-03-25-0/+167
| | | | | | This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: split COBJS onto separate linesAnton Vorontsov2008-03-25-11/+12
| | | | | | ..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: nand support for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+19
| | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.Jerry Van Baren2008-03-25-0/+1
| | | | | Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc8323erdb: remove RTC and add EEPROMMichael Barkowski2008-03-25-3/+4
| | | | | | | There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* mpc8323erdb: Improve the system performanceMichael Barkowski2008-03-25-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* mpc8323erdb: use readable DDR config macrosMichael Barkowski2008-03-25-8/+42
| | | | | | | Use available shift/mask macros to define DDR configuration. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Add Vitesse VSC7385 firmware uploadingTimur Tabi2008-03-25-71/+196
| | | | | | | | | | Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* NET: Add Vitesse VSC7385 firmware uploadingTimur Tabi2008-03-25-0/+115
| | | | | | | | | | | | | | | The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX and other boards. A small firwmare must be uploaded to its on-board memory before it can be enabled. This patch adds the code which uploads firmware (but not the firmware itself). Previously, this feature was provided by a U-Boot application that was made available only on Freescale BSPs. The VSC7385 firmware must still be obtained separately, but at least there is no longer a need for a separate application. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
* Coding Style cleanyp; update CHANGELOGWolfgang Denk2008-03-26-56/+832
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk2008-03-26-455/+1058
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| * [MIPS] Move gth2_config from ARM section to MIPSShinya Kuribayashi2008-03-25-5/+5
| | | | | | | | Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kBShinya Kuribayashi2008-03-25-5/+9
| | | | | | | | Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Fix dcache_status()Shinya Kuribayashi2008-03-25-3/+7
| | | | | | | | | | | | You can't judge UNCACHED by Config.K0 LSB. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Introduce _machine_restartShinya Kuribayashi2008-03-25-8/+42
| | | | | | | | | | | | Handles machine specific functions by using weak functions. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Cleanup CP0 Status initializationShinya Kuribayashi2008-03-25-9/+25
| | | | | | | | | | | | | | | | Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Initialize CP0 Cause before setting up CP0 Status registerShinya Kuribayashi2008-03-25-3/+3
| | | | | | | | | | | | | | Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()Shinya Kuribayashi2008-03-25-8/+6
| | | | | | | | | | | | Move things to appropriate place. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Implement flush_cache()Shinya Kuribayashi2008-03-25-0/+22
| | | | | | | | | | | | | | | | | | We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you don't need to do Hit_Invalidate_I, but flush_cache() needs it since this function is used not only in U-Boot specfic programs but also at loading target binaries. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Fix I-/D-cache initialization loopsShinya Kuribayashi2008-03-25-39/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we're encouraged to use three separate loops rather than combining them *for both I- and D-cache*. This patch tries to fix this. In accordance with fixing above, mips_init_[id]cache are separated from mips_cache_reset(), and rewrite cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Replace memory clearance code with f_fill64Shinya Kuribayashi2008-03-25-15/+28
| | | | | | | | | | | | This routine fills memory with zero by 64 bytes, and is 64-bit capable. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macrosShinya Kuribayashi2008-03-25-18/+416
| | | | | | | | | | | | | | | | | | | | This patch replaces the current function definitions with NESTED, LEAF and END macro. They specify some more additional information about the function; an alignment of symbol, type of symbol, stack frame usage, etc. These information explicitly tells the assembler and the debugger about the types of code we want to generate. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] asm headers' updatesShinya Kuribayashi2008-03-25-343/+416
| | | | | | | | | | | | Make some asm headers adjusted to the latest Linux kernel. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Request for the 'mips_cache_lock()' removalShinya Kuribayashi2008-03-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial intension of having mips_cache_lock() was to use the cache as memory for temporary stack use so that a C environment can be set up as early as possible. But now mips_cache_lock() follow lowlevel_init(). We've already have the real memory initilaized at this point, therefore we could/should use it. No reason to lock at all. Other problems: Cache locking is not consistent across MIPS implementaions. Some imple- mentations don't support locking at all. The style of locking varies - some support per line locking, others per way, etc. Some parts use bits in status registers instead of cache ops. Current mips_cache_lock() is not necessarily general-purpose. And this is worthy of special mention; once U-Boot/MIPS locks the lines, they are never get unlocked, so the code relies on whatever gets loaded after U-Boot to re-initialize the cache and clear the locks. We're sup- posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, but leave the situation as it is for a long time. For these reasons, I proposed the removal of mips_cache_lock() from the global start-up code. This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that *things have changed*. If he wants the same behavior as before, he needs to have CFG_INIT_RAM_LOCK_MIPS in his config file. If we don't have any regression report through several releases, then we'll remove codes entirely. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Acked-by: Andrew Dyer <amdyer@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-03-26-0/+0
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| * | FSL: Move board/mpc7448hpc2 under board/freescaleJon Loeliger2008-03-25-1/+1
| | | | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | FSL: Move board/mpc8266ads under board/freescaleJon Loeliger2008-03-25-1/+1
| | | | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | FSL: Move board/mpc8260ads under board/freescaleJon Loeliger2008-03-25-3/+3
| |/ | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_TJerry Van Baren2008-03-26-234/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These defines embedded the u-boot env variables and/or the bd_t structure in the fdt blob. The conclusion of discussion on the u-boot email list was that embedding these in the fdt blob is not useful: there are better ways of passing the data (in fact, the fdt blob itself replaces the bd_t struct). The only board that enables these is the stxxtc and they don't appear to be used by linux. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | rtc: Remove 2nd reference to max6900.o in drivers/rtc/MakefileStefan Roese2008-03-26-1/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Add Flex-OneNAND booting supportKyungmin Park2008-03-26-17/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that would otherwise have to use more NOR components. Flex-OneNAND enables users to configure to partition it into SLC and MLC areas in more flexible way. While MLC area of Flex-OneNAND can be used to store data that require low reliability and high density, SLC area of Flex-OneNAND to store data that need high reliability and high performance. Flex-OneNAND can let users take advantage of storing these two different types of data into one chip, which is making Flex-OneNAND more cost- and space-effective. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | MPC5200: support setup without FECAndré Schwarz2008-03-25-0/+4
| | | | | | | | | | | | | | | | Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is defined. Systems without FEC, i.e. no FEC node in DTB, should be possible. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | FSL: Move board/mpc8266ads under board/freescaleJon Loeliger2008-03-25-1/+1
| | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | FSL: Move board/mpc7448hpc2 under board/freescaleJon Loeliger2008-03-25-1/+1
| | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | FSL: Move board/mpc8260ads under board/freescaleJon Loeliger2008-03-25-3/+3
| | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | net: Add support AX88796L ethernet devicegoda.yusuke2008-03-25-0/+223
| | | | | | | | | | | | | | | | AX88796L is device of NE2000 compatible. This patch support AX88796L ethernet device. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ne2000 driver: change #ifdef to Makefile conditional compilationWolfgang Denk2008-03-25-4/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | net: Divided code of NE2000 ethernet drivergoda.yusuke2008-03-25-355/+456
| | | | | | | | | | | | | | | | | | There are more devices of the NE2000 base. A present code is difficult for us to support more devices. To support more NE2000 clone devices, separated the function. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | net/Blackfin: move on-chip MAC driver into drivers/net/Mike Frysinger2008-03-25-104/+97
| | | | | | | | | | | | | | | | The Blackfin on-chip MAC driver was being managed in the BF537-STAMP board directory, but it is not board specific, so relocate it to the drivers dir so that other Blackfin ports can utilize it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | smc91111: use SSYNC() rather than asm(ssync) for BlackfinMike Frysinger2008-03-25-2/+2
| | | | | | | | | | | | | | | | Since the "ssync" instruction may have hardware anomalies associated with it, have the smc91111 driver use the SSYNC macro rather than invoking it directly. We workaround all the anomalies via this macro. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | 8xx: Update OF support on 8xxBryan O'Donoghue2008-03-25-13/+76
| | | | | | | | | | | | This patch does some shifting around of OF support on 8xx. Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
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