summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* ppc/85xx: Convert MPC8536DS to using board common ICS307 codeKumar Gala2010-07-16-157/+6
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Convert MPC8572DS to using board common ICS307 codeKumar Gala2010-07-16-153/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add command to report errata workaroundsKumar Gala2010-07-16-3/+55
| | | | | | | | | Add 'errata' command to report what errata we workaround. Report workaround for erratum SATA-A001 on P1022/P1013. Also sorted the CONFIG_CMD_* list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: add support for the Freescale P1022DS reference boardTimur Tabi2010-07-16-0/+1184
| | | | | | | | | | | | | Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2_rdb: PCIe E1000 card support added.Poonam Aggrwal2010-07-16-0/+1
| | | | | | | | Enables the Intel Pro/1000 PT Gb Ethernet PCI-E Network Adapter configuration support for P1/P2 RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: add LAW target to fsl_pci_info structureTimur Tabi2010-07-16-8/+11
| | | | | | | | | | | | | Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for link stack & STAC on e5500Kumar Gala2010-07-16-1/+3
| | | | | | | | The e5500 has a link register stack and segment target address cache. Its safe to enable these bits on older e500 cores as the bits are implemented in the register. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add recognition of e5500 coreKumar Gala2010-07-16-10/+18
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc 83xx/85xx: Merge lbc upmconfig codeBecky Bruce2010-07-16-127/+53
| | | | | | | | | | Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add reginfo commandBecky Bruce2010-07-16-0/+41
| | | | | | | | The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law.c: Add print_laws() for FSL_CORENET platforms.Becky Bruce2010-07-16-0/+6
| | | | | | | Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms. Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/misc/fsl_law.c: Rearrange code to avoid duplicationBecky Bruce2010-07-16-77/+49
| | | | | | | | The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add print_tlbcam() functionBecky Bruce2010-07-16-0/+21
| | | | | | | This dumps out the contents of TLB1 on 85xx-based systems. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: tlb.c cleanupsBecky Bruce2010-07-16-26/+25
| | | | | | | | | | | Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-500/+318
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Update configs to properly set FSL_ELBCBecky Bruce2010-07-16-0/+6
| | | | | | | | | | | Some parts that have an Enhanced Local Bus Controller weren't setting CONFIG_FSL_ELBC. Fix this so we can use this define properly going forward (currently it's only used if PHYS_64BIT is set, which meant not all platforms needed to have it set correctly). Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2_rdb: enable hwconfigPoonam Aggrwal2010-07-16-0/+2
| | | | | Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Move ICS CLK chip frequency calculation code into a common board libraryKumar Gala2010-07-16-160/+124
| | | | | | | | | | | | We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com>
* ppc/85xx: Add a structure defn for PIXIS registersKumar Gala2010-07-16-1/+183
| | | | | | | | | | | | | The various boards that have PIXIS FPGAs have slightly different register definitions, however there is some common functionality (like reset, ICS307 clk control, etc) that can be shared. The struct definition exists for MPC8536DS, MPC8544DS, MPC8572DS, MPC8610HPCD, and MPC8641HPCN boards. Also fixed ngpixis to be __packed__ instead of aligned. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtbKumar Gala2010-07-16-7/+50
| | | | | | | If we explicitly disabled a core remove it from the dtb we pass on to the kernel. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Remove cpu-handles for cpus we deleteKumar Gala2010-07-16-6/+30
| | | | | | | We may have cpu-handles pointing to the cpu nodes we delete. If so we should delete the handles as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add base support for the SEC4Kim Phillips2010-07-16-1/+47
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Distinguish between incompatible SEC h/w typesKim Phillips2010-07-16-4/+11
| | | | | | | | | CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: move fsl specific code from common fdt area to mpc8xxx/fdt.cKim Phillips2010-07-16-132/+138
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2010-07-14-1054/+49
|\
| * nios2: remove EP1C20, EP1S10, EP1S40 boardsThomas Chou2010-07-12-1046/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The example configuration files of nios2-generic board can generated binary to run on the EP1C20, EP1S10, and EP1S40 boards. So the three boards can be removed. With nios2-generic approach, the fpga parameter header file can be generated from hardware designs using tools. Porting u-boot for nios2 boards is simplified. Vendors can supply their fpga parameter file or patches to add a new nios2-generic board instance. There is no need to include other boards support for nios2 in the u-boot mainline. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: add spi flash support to nios2-generic boardThomas Chou2010-07-12-0/+10
| | | | | | | | | | | | | | | | | | | | This patch enables the altera_spi and spi_flash drivers for the nios2-generic board. It allows access to the EPCS/SPI flash on the Altera EP1C20 board. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * gpio_led: add gpio_request to __led_initThomas Chou2010-07-12-8/+4
| | | | | | | | | | | | | | | | This patch adds the gpio usage request. The polarity is changed to positive as suggested by Mike Frysinger. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: add gpio_requestThomas Chou2010-07-12-0/+11
| | | | | | | | | | | | | | This will be used by nand_plat. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: add fdt supportThomas Chou2010-07-12-0/+21
| | | | | | | | | | | | | | | | This patch adds fdt support to boot linux, followed Michal's work on microblaze. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: use gc sections to reduce image sizeThomas Chou2010-07-12-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the discussion of Charles Manning and Mike Frysinger. Using gc_sections helps reduce image size. Configuring for nios2-generic board... Before, text data bss dec hex filename 123979 3724 22892 150595 24c43 /tmp/u-boot/u-boot After, text data bss dec hex filename 115983 3800 22732 142515 22cb3 /tmp/u-boot/u-boot Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-07-14-21/+1745
|\ \
| * | 83xx: add support for ve8313 boardHeiko Schocher2010-07-09-0/+786
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for the ve8313 board based on Freescale MPC8313 CPU. - serial console on UART 1 - 128 MB DDR RAM - 32 MB NOR Flash - 16 MB NAND Flash - Ethernet MII Mode over on TSEC0 - micrel ksz804 phy - Hardware WDT MAX824 changes since v1 - Environment size = sector size - use red. environment - add comments from Kim Phillips - add MAKEALL, MAINTAINERS entry - Codingstyle issues fixed - inserted original Copyrights - PCI subsys vendor ID changed from 0x1057 (Motorola) to 0x1957 (Freescale) changes since v2 - add comments from Wolfgang Denk - fix Codingstyle and some comments - reworked WDT reset (just toggling the WD_TRIG pin) - Environment size now 16KiB - fixed RAMBOOT version - fixed CONFIG_SYS_LOAD_ADDR - renamed CONFIG_TSEC1_NAME to TSEC1 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | MPC8308RDB: minimal support for devboard from FreescaleIlya Yanok2010-07-09-0/+905
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for MPC8308RDB development board from Freescale with a minimal set of features: Dual UART is supported NOR flash is supported Both TSEC Ethernet controllers are supported PCI Express initialization is supported The following features are enabled in configuration but not fully tested: I2C (used to get the board revision) I2C-connected RTC VSC7385 switch There is one (hopefully) minor issue: on soft reset the board sometimes resets twice. I've not managed to find the fix for this problem yet. As a workaround instruction cache can be disabled. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc8308: support for Freescale MPC8308 cpuIlya Yanok2010-07-09-21/+54
| |/ | | | | | | | | | | | | | | | | | | This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch). Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2010-07-14-907/+1898
|\ \
| * | edminiv2: add ethernet supportAlbert Aribaud2010-07-12-4/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add edminiv2 board support for mv_egiga. Add edminiv2 config to enable mv_egiga. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | mvgbe: add support for orion5x GbE controllerAlbert Aribaud2010-07-12-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add definitions and initialization in orion5x for mvgbe. Add orion5x in mvgbe SoC includes. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | mvgbe: support SoCs other than kirkwoodAlbert Aribaud2010-07-12-416/+439
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename all references to kirkwood in mvgbe symbols throughout the whole codebase. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | net: rename: kirkwood_egiga as mvgbeAlbert Aribaud2010-07-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename kirkwood_egiga.* to mvgbe.* and adjust makefile and #include accordingly. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | kirkwood_egiga: CONFIG_SKIP_LOCAL_MAC_RANDOMIZATIONAlbert Aribaud2010-07-12-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This configuration option allows SoCs without random generation capability to fill in local MACs with a fixed rather than random value Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | cpuat91: unbreak ethernetEric Bénard2010-07-12-16/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * the following problems are met : config was set to use the new driver as a default but - RMII was not enabled for the new driver - the new driver didn't compile with RMII enabled - the new driver initialize a PHY at address O when the PHY of this board is at 1 thus we get "AT91 EMAC RMII: No PHY present" * to fix these problems, this patch : - enable RMII for the new driver - fix the wrong define used in the at91_emac.c - allow the config file to set a default phy address (and use 0 as a default as in the actual at91_emac.c driver) Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | at91_emac: Write MAC address automaticallyEric Bénard2010-07-12-8/+20
| | | | | | | | | | | | | | | | | | | | | tested on cpuat91. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | AX88180: use standard I/O accessorsMike Frysinger2010-07-12-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current dm9000x driver accesses its memory mapped registers directly instead of using the standard I/O accessors. This can cause problems on Blackfin systems as the accesses can get out of order. So convert the direct volatile dereferences to use the normal in/out macros. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Hoan Hoang <hnhoan@i-syst.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | AX88180: make OUTW handle 32bit/16bit defines tooHoan Hoang2010-07-12-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current OUTW function is always defined as a 16bit function, but this doesn't work correctly when using the 32bit access mode. So define it as a 32bit function when in 32bit mode so things work correctly on Blackfin 32bit LE systems. Signed-off-by: Hoan Hoang <hnhoan@i-syst.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | AX88180: add support for the Marvell 88E1118 phyHoan Hoang2010-07-12-12/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some places in the current code equate the Marvell 88E1111 PHY as the family when in reality it's a subpart of the Alaska family. So once we generalize that, add support for the 88E1118 PHY. Signed-off-by: Hoan Hoang <hnhoan@i-syst.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | Write MAC address automatically on MACB-based boardsBen Warren2010-07-12-64/+15
| | | | | | | | | | | | | | | | | | Also, remove all calls to eth_init() in boards that use MACB Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | smc91xx_eeprom: Correct chip detection check.Juergen Kilb2010-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smc911x_detect function in /net/driver/net/smc911x.c returns a 0 if everything was ok (a chip was found) and -1 else. In the standalone example 'smc911x_eeprom' the return value of smc911x_detect is interpreted in a different way (0 for error, !0 as OK). This leads to the error that the chip will not be detected. Signed-off-by: Juergen Kilb <j.kilb@phytec.de> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | tsec: fix the return value for tsec_eth_init()Timur Tabi2010-07-12-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ethernet initialization functions are supposed to return the number of devices initialized, so fix tsec_eth_init() so that they returns the number of TSECs initialized, instead of just zero. This is safe because the return value is currently ignored by all callers, but now they don't have to ignore it. In general, if an function initializes only one device, then it should return a negative number if there's an error. If it initializes more than one device, then it should never return a negative number. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | uli526x: drop newlines from device nameMike Frysinger2010-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | Device names should not contain non-printable characters like newlines. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
generated by cgit v1.1 at 2024-12-16 18:19:24 +0000