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* 83xx: add missing TIMING_CFG1_CASLAT_* definesHeiko Schocher2009-02-16-0/+2
| | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc8349itx: allow SATA boot from the onboard SIL1334Valeriy Glushkov2009-02-16-2/+21
| | | | | | | | This patch allows using of SATA devices connected to the onboard PCI SIL1334 SATA controller. Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Add eSDHC support on 8379 EMDS boardAndy Fleming2009-02-16-5/+52
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+46
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add support for the Freescale eSDHC found on 8379 and 8536 SoCsAndy Fleming2009-02-16-0/+494
| | | | | | | | This uses the new MMC framework Some contributions by Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add MMC FrameworkAndy Fleming2009-02-16-9/+1253
| | | | | | | | | | | | | | Here's a new framework (based roughly off the linux one) for managing MMC controllers. It handles all of the standard SD/MMC transactions, leaving the host drivers to implement only what is necessary to deal with their specific hardware. This also hooks the infrastructure into the PowerPC board code (similar to how the ethernet infrastructure now hooks in) Some of this code was contributed by Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminated arch-specific mmc header requirementAndy Fleming2009-02-16-100/+54
| | | | | | | | | | The current MMC infrastructure relies on the existence of an arch-specific header file. This isn't necessary, and a couple drivers were forced to implement dummy files to meet this requirement. Instead, we move the stuff in those header files into a more appropriate place, and eliminate the stubs and the #include of asm/arch/mmc.h Signed-off-by: Andy Fleming <afleming@freescale.com>
* Convert mmc_init to mmc_legacy_initAndy Fleming2009-02-16-6/+6
| | | | | | This is to get it out of the way of incoming MMC framework Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminate support for using MMC as memoryAndy Fleming2009-02-16-99/+0
| | | | | | MMC cards are not memory, so we stop treating them that way. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-1/+25
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* TQM85xx: Fix a couple warnings in TQM8548 buildAndy Fleming2009-02-16-3/+5
| | | | | | | | | | | | The ecm variable in sdram.c was being declared for all 8548, but only used by specific 8548 boards, so we make that variable require those specific boards, too The nand code was using an index "i" into a table, and then re-using "i" to set addresses for each upm. However, then it relied on the old value of i still being there to enable things. Changed the second "i" to "j" Signed-off-by: Andy Fleming <afleming@freescale.com>
* MPC85xx: TQM8548: workaround for erratum DDR 19 and 20Wolfgang Grandegger2009-02-16-8/+108
| | | | | | | | | This patch adds the workaround for erratum DDR20 according to MPC8548 Device Errata document, Rev. 1: "CKE signal may not function correctly after assertion of HRESET". Furthermore, the bug DDR19 is fixed in processor version 2.1 and the work-around must be removed. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: use cache for AG and BE variantsWolfgang Grandegger2009-02-16-2/+2
| | | | | | | | | | | | This patch makes accesses to the system memory cachable by removing the caching-inhibited and guarded flags from the relevant TLB entries for the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards are configured similarly. This results in a big averall performace improvement. TFTP downloads, NAND Flash accesses, kernel boots, etc. are much faster. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configurationWolfgang Grandegger2009-02-16-4/+26
| | | | | | | | This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG module. Signed-off-by: Jens Gehrlein <sew_s@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: fix SDRAM timing for 533 MHzWolfgang Grandegger2009-02-16-6/+8
| | | | | | | | | | According to new TQM8548 timing specification: Refresh Recovery: 34 -> 53 clocks CKE pulse width: 1 -> 3 cycles Window for four activities: 13 -> 14 cycles Signed-off-by: Jens Gehrlein <sew_s@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: add support for the TQM8548_AG moduleWolfgang Grandegger2009-02-16-3/+12
| | | | | | | | The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory, CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module with "$ make TQM8548_AG_config". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: add support for the TQM8548_BE moduleWolfgang Grandegger2009-02-16-8/+22
| | | | | | | | | The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: make standard PCI/PCI-X configurableWolfgang Grandegger2009-02-16-10/+11
| | | | | | | | | The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: fix flash protection for boot loaderWolfgang Grandegger2009-02-16-2/+1
| | | | | | | | | | | | | | | | | | | | As the reset vector is located at 0xfffffffc, all flash sectors from the beginning of the U-Boot binary to 0xffffffff must be protected. On the TQM8548-AG having small sectors at the end of the flash it happened that the last two sector were not protected and an "erase all" left an un-bootable system behind: Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E Erase timeout: 8192 ms, write timeout: 1 ms FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000 The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many board BSPs as well. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 86xx: Update CPU info output on bootupPeter Tyser2009-02-16-42/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Update Global Utilities structurePeter Tyser2009-02-16-8/+21
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Reset updatePeter Tyser2009-02-16-65/+64
| | | | | | | | | | Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala2009-02-16-1/+1
| | | | | | | | | | Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report an error and hang. Instead of doing that since DDR is mapped in the lowest priority LAWs we setup the DDR controller and the max amount of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED) Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-5/+32
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DSKumar Gala2009-02-16-2/+6
| | | | | | | | Added some info that is printed out when we boot to distiquish if we built MPC8572DS_config vs MPC8572DS_36BIT_config since they have different address maps. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fixup SGMII PHY ids in the device treeAndy Fleming2009-02-16-0/+79
| | | | | | | | | | | The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card. The 8572, 8536, and 8544 DS boards were modified to call this function. Code idea taken from Liu Yu <yu.liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Make some minor whitespace changes to eliminate line-wrappingAndy Fleming2009-02-16-15/+16
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add eth_get_dev_by_indexAndy Fleming2009-02-16-0/+22
| | | | | | This allows code to iterate through the ethernet devices Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix bug in device tree setup in 36-bit physical confgKumar Gala2009-02-16-1/+2
| | | | | | | | | | In the 36-bit physical config for MPC8572DS when need the start address of memory and it size to be kept in phys_*_t instead of a ulong since we support >4G of memory in the config and ulong cant represent that. Otherwise we end up seeing the memory node in the device tree reporting back we have memory starting @ 0 and of size 0. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix address map for 36-bit config of MPC8572DSKumar Gala2009-02-16-5/+10
| | | | | | | | | | When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-48/+31
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-16-0/+4
| | | | | | | | If we only have one controller we can completely ignore how memctl_intlv_ctl is set. Otherwise other levels of code get confused and think we have twice as much memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
| | | | | | | Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2009-02-15-12/+11
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| * USB: Remove LUN number from CDBAbraham, Thomas2009-02-15-5/+0
| | | | | | | | | | | | | | The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB. Signed-off-by: Thomas Abraham <t-abraham@ti.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * Added usbtty_configured() check. Fixed attribute(packed) warnings.Atin Malaviya2009-02-15-7/+11
| | | | | | | | | | | | | | | | | | | | | | V3: Fixed line-wrap problem due to user error in mail! Added usb_configured() checks in usbtty_puts() and usbtty_putc() to get around a hang when usb is not connected and the user has set up multi-io (setenv stdout serial,usbtty etc). Got rid of redundant __attribute__((packed)) directives that were causing warnings from gcc. Signed-off-by: Atin Malaviya <atin.malaviya@gmail.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2009-02-15-14/+6
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| * i.MX31: Start the I2C clock on driver initialisationGuennadi Liakhovetski2009-02-14-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | i.MX31 powers on with most clocks running, so, after a power on this explicit clock start up is not required. However, as Linux boots it disables most clocks to save power. This includes the I2C clock. If we then soft reboot from Linux the I2C clock stays off. This breaks the phycore, which has its environment in I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver initialisation routine. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Ack-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * i2c.h: drop i2c_reg_{read, write} hack for Blackfin partsMike Frysinger2009-02-12-14/+0
| | | | | | | | | | | | | | The Blackfin i2c driver has been rewritten thus the special ifdefs in the common code are no longer needed. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-02-12-44/+59
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| * | ppc4xx: Add README entry for CONFIG_PCI_DISABLE_PCIEDirk Eibach2009-02-12-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix initialization of the SDRAM_CODT registerCarolyn Smith2009-02-12-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boardsStefan Roese2009-02-12-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Some AMCC eval boards do have a board_eth_init() function calling pci_eth_init(). These boards need to call cpu_eth_init() explicitly now with the new eth_init rework. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-36/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.hStefan Roese2009-02-12-3/+2
| |/ | | | | | | | | | | | | | | | | | | CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB. It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx boards right now. Signed-off-by: Stefan Roese <sr@denx.de>
* | 82xx, mgcoge: fix compile errorHeiko Schocher2009-02-12-0/+1
|/ | | | | | | | | | | | With actual u-boot compiling the mgcoge port fails, because since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is necessary to define CONFIG_NET_MULTI. Seems to me the mgcoge port is the only actual existing 8260 port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed to be fixed. Signed-off-by: Heiko Schocher <hs@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-02-12-54/+2440
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add feature-removal-schedule.txtPeter Tyser2009-02-11-0/+37
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 8xx serial, smc: Coding-Style cleanup serial SMC driverHeiko Schocher2009-02-11-48/+24
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* 8xx serial, smc: add configurable SMC Rx buffer lenHeiko Schocher2009-02-11-38/+58
| | | | | | | | | | | | | | This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN. With this option it is possible to allow the receive buffer for the SMC on 8xx to be greater then 1. In case CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the old version. When defining CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined to setup the maximum idle timeout for the SMC. Signed-off-by: Heiko Schocher <hs@denx.de>
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