summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* mpc8610hpcd: Use common 86xx fdt fixup codePeter Tyser2009-09-24-13/+1
| | | | | | | | Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc85x0: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-24-29/+25
| | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: allow enabling PCI via a make config optionPaul Gortmaker2009-09-24-12/+43
| | | | | | | | | | | | | | Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: update PCI/PCI-e support codePaul Gortmaker2009-09-24-143/+96
| | | | | | | | | | | | | | | | | | The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: create a SET_STD_PCI_INFO() helper wrapperPaul Gortmaker2009-09-24-0/+12
| | | | | | | | Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: correct local bus SDRAM size from 64M to 128MPaul Gortmaker2009-09-24-12/+61
| | | | | | | | | | | The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: use I/O accessorsPaul Gortmaker2009-09-24-46/+45
| | | | | | | | Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: remove eTSEC3/4 voltage hackPaul Gortmaker2009-09-24-6/+0
| | | | | | | | With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: enable access to second bank of flashPaul Gortmaker2009-09-24-7/+29
| | | | | | | | | | | | | | | | | | | The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: cosmetic line re-wrapPaul Gortmaker2009-09-24-4/+8
| | | | | | | Fix the extra long lines to be consistent with u-boot coding style. No functional change here. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8548: get_clock_freq is not valid for this boardPaul Gortmaker2009-09-24-3/+3
| | | | | | | | | | | The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: delete unused MPC8548CDS info carried over from portPaul Gortmaker2009-09-24-66/+6
| | | | | | | | | | | | | | | | | | There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: enable use of PCI network cardsPaul Gortmaker2009-09-24-0/+9
| | | | | | | | | Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: 32bit DDR changes for P1020/P1011Poonam Aggrwal2009-09-24-5/+24
| | | | | | | | | | | | | The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: replace README with completely new documentPaul Gortmaker2009-09-24-23/+173
| | | | | | | | | | | | | The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up use of LAWAR definesKumar Gala2009-09-24-31/+26
| | | | | | | | | On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up mpc8572DS PCI setup codeKumar Gala2009-09-24-157/+73
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up p2020ds PCI setup codeKumar Gala2009-09-24-117/+33
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up p1_p2_rdb PCI setupKumar Gala2009-09-24-21/+23
| | | | | | | | General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Simplify the top makefile for P1_P2_RDB boardsKumar Gala2009-09-24-18/+17
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Simplify the top makefile for 36-bit config for P2020DSKumar Gala2009-09-24-6/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DSKumar Gala2009-09-24-6/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: simplify the top makefile for 36-bit config for mpc8536dsMingkai Hu2009-09-24-4/+2
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix LCRR_CLKDIV definesKumar Gala2009-09-24-3/+11
| | | | | | | | | | | | | | | | | | | | | For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-25/+43
|\
| * Merge branch 'master' of git://git.denx.de/u-boot-ubiWolfgang Denk2009-09-24-25/+43
| |\
| | * ubifs: Add support for looking up directory and relative symlinksSimon Kagstrom2009-09-23-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for resolving symlinks to directories as well as relative symlinks. Symlinks are now always resolved during file lookup, so the load stage no longer needs to special-case them. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-18/+25
|\ \ \ | |/ /
| * | ppc4xx: Fix PCIE PLL lock on 440SPe Yucca boardRupjyoti Sarmah2009-09-23-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Make DDR2 timing for intip more robustDirk Eibach2009-09-23-10/+10
| |/ | | | | | | | | | | | | | | DDR2 timing for intip was on the edge for some of the available chips for this board. Now it is verfied to work with all of them. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | board/linkstation/ide.c: Fix compile warningWolfgang Denk2009-09-22-2/+4
| | | | | | | | | | | | | | | | Fix warning: ide.c:60: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Guennadi Liakhovetski <lg@denx.de>
* | ppc: Clean up calling of phy_reset() during initPeter Tyser2009-09-22-16/+18
| | | | | | | | | | | | | | Remove board-specific #ifdefs for calling phy_reset() during initializtion Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | ppc: Clean up calling of misc_init_r() during initPeter Tyser2009-09-22-13/+16
| | | | | | | | | | | | | | | | Remove board-specific #ifdefs for calling misc_init_r() during initializtion Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Heiko Schocher <hs@denx.de>
* | Remove deprecated 'autoscr' command/variablesPeter Tyser2009-09-22-124/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The more standard 'source' command provides identical functionality to the autoscr command. Environment variable names/values on the MVBC_P, MVBML7, kmeter1, mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. The 'autoscript' and 'autoscript_uname' environment variables are also removed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Heiko Schocher <hs@denx.de>
* | mpc512x. Micron nand flash needs a reset before a read command is issued.Paul Gibson2009-09-22-0/+1
| | | | | | | | | | Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
* | FDT: remove obsolete OF_CPU and OF_SOC macros.Marcel Ziswiler2009-09-22-13/+4
|/ | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Heiko Schocher <hs@denx.de>
* board/flagadm/flash.c: fix compile warningWolfgang Denk2009-09-18-3/+9
| | | | | | | | Fix warning: flash.c:531: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Kári Davíđsson <kd@flaga.is>
* Merge branch 'warning-cleanup'Wolfgang Denk2009-09-18-1/+1
|\
| * kwbimage.c: Fix compile warning when building on 64 bit systems (again)Wolfgang Denk2009-09-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | Commit 51003b89 attempted to fix a build problem on 64 bit systems, but just turned it into a build problem on 32 bit systems (silly me). Now do the Right Thing (TM) and use a "%zu" printf format. Also fix spelling error. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-17-77/+22
|\ \
| * | ppc4xx: Consolidate get_OPB_freq()Stefan Roese2009-09-17-75/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Enable commands for FDT enabled Linux booting on AMCC AcadiaStefan Roese2009-09-17-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Acadia still used the "old" arch/ppc bootm commands for booting Linux images without FDT. This patch now enables these fdt-aware boot commands for Acadia as well. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix 405EZ uart base baud calculationStefan Roese2009-09-17-1/+5
| | | | | | | | | | | | | | | | | | | | | With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Correct ffs/fls regression for PowerPC etcSimon Kagstrom2009-09-17-41/+15
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* | ppc/85xx: Disable all async interrupt sources when we bootKumar Gala2009-09-15-0/+11
| | | | | | | | | | | | | | | | We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Split out cpu_init_early into its own file for NAND_SPLKumar Gala2009-09-15-51/+77
| | | | | | | | | | | | | | By pulling out cpu_init_early we can build just it and not all of cpu_init for NAND_SPL. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Change cpu_init_early_f so we can use with NAND SPLKumar Gala2009-09-15-9/+25
| | | | | | | | | | | | | | Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | NAND boot: change NAND loader's relocate SP to CONFIG paramMingkai Hu2009-09-15-2/+4
| | | | | | | | | | | | | | | | | | | | So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-1/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move code around to prep for NAND_SPLKumar Gala2009-09-15-23/+23
| | | | | | | | | | | | | | | | If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-26 15:18:30 +0000