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* Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2010-01-12-15/+1415
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| * usb: musb: add virtual root hub control supportBryan Wu2010-01-12-2/+482
| | | | | | | | | | | | | | | | | | For MUSB devices that do not support multipoint (hubs), we have to emulate a root hub so that we can support core operations like resetting ports. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Adds EHCI definitions to sequoia board configuration file.Chris Zhang2010-01-09-1/+15
| | | | | | | | | | | | | | Adds required definitions for EHCI support in sequoia configuration file. But still keeps the OHCI as default driver. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * Add ppc440epx USB ehci support.Chris Zhang2010-01-09-0/+49
| | | | | | | | | | | | | | Currently ppc440epx uses OHCI for USB full-speed support. This change adds support for EHCI. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * Fix EHCI port reset.Chris Zhang2010-01-09-0/+3
| | | | | | | | | | | | | | | | | | In USB ehci driver, the port reset is not terminated. EHCI spec says "A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds". Without termination, a port stays at reset state. This is observed on ppc4xx(sequoia) boards. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * omap3: fix compile warningSanjeev Premi2010-01-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | This patch fixes this warning during compile: omap3.c: In function 'musb_platform_init': omap3.c:126: warning: label 'end' defined but not used Problem reported by: Dirk Behme[dirk.behme@googlemail.com] Signed-off-by: Sanjeev Premi <premi@ti.com>
| * usb: musb: add support for Blackfin MUSBBryan Wu2010-01-09-2/+528
| | | | | | | | | | | | | | Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * usb: musb: change rxcsr register from write to read/modify/writeBryan Wu2010-01-09-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The RX Control/Status register has bits that we want to preserve, so don't just write out a single bit. Preserve the others bits in the process. The original code posted to the u-boot list had this behavior, but looks like it was lost somewhere along the way to merging. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * usb: musb: make multipoint optionalBryan Wu2010-01-09-0/+20
| | | | | | | | | | | | | | | | | | | | The multipoint handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * usb: musb: make fifo support configurableBryan Wu2010-01-09-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The dynamic FIFO handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Due to this, the FIFO reading/writing steps need special handling, so mark the common versions weak so drivers can override. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * usb: musb: make sure the register layout is packedMike Frysinger2010-01-09-1/+1
| | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * DA830: Add usb configAjay Kumar Gupta2010-01-09-5/+33
| | | | | | | | | | | | | | Adding USB configuration. Default is set for USB MSC host. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * DA8xx: Add MUSB host supportAjay Kumar Gupta2010-01-09-1/+244
| | | | | | | | | | | | | | Tested USB host functionality on DA830 EVM. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * DA8xx: Add GPIO register definitionsAjay Kumar Gupta2010-01-09-0/+14
| | | | | | | | | | | | | | | | Added DA8xx GPIO base addresses in gpio_defs.h and pointers to different BANKs which can be used to program GPIOs. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * DA830: Add pinmux for USB0_DRVVBUSAjay Kumar Gupta2010-01-09-0/+8
| | | | | | | | | | | | | | | | USB0_DRVVBUS pinmux configuration is required for USB functinality in uboot. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-01-12-131/+455
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| * | mpc83xx: add support configure bus parkingHeiko Schocher2010-01-07-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: vme8349: Fix power up reset sequence for tsi148Reinhard Arlt2010-01-07-8/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove PCI reset, if there is a monarch PMC module. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: Add support for MPC8349 esd caddy2Reinhard Arlt2010-01-07-100/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The caddy2 is a variant of the already supported vme8349. So we just add the differences to this board port. To better support those two boards we switched from fixed SDRAM configuration to usage of spd_sdram(). This is done by providing a board specific SPD EEPROM routine with different values for both boards. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> changed to use mkconfig -t option instead, plus misc codingstyle fixes. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: spd_sdram.c: Disable memory controller before initializingStefan Roese2010-01-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: Add NAND boot support for MPC8315E-RDB boardsAnton Vorontsov2010-01-07-23/+167
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | ppc/p4080: Add Corenet Platform Cache (CPC) registersBecky Bruce2010-01-05-0/+75
| | | | | | | | | | Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-3/+8
| | | | | | | | | | | | | | | | | | Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: add the override for write levelingDave Liu2010-01-05-7/+21
| | | | | | | | | | | | | | | | add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: Fix power-down timing settingsDave Liu2010-01-05-3/+4
| | | | | | | | | | | | | | | | | | | | | | 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2010-01-05-0/+18
| | | | | | | | | | | | | | | | | | Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/p4080: Fix reporting of PME & FM clock frequenciesKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_law: add SRIO2 target id and law_size_bits() macroLi Yang2010-01-05-0/+3
| | | | | | | | | | Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc: Added macro to test for specific SVR revisionKumar Gala2010-01-05-0/+3
| | | | | | | | | | | | | | Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | p4080: add readback to bootpage translation windowDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | | | We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Make flash TLB entry determined at runtime on FSL boardsKumar Gala2010-01-05-4/+4
| | | | | | | | | | | | | | Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Remove CONFIG_SYS_DDR_TLB_STARTKumar Gala2010-01-05-4/+0
| | | | | | | | | | | | | | Now that we dynamically determine TLB CAM entries to use we dont need CONFIG_SYS_DDR_TLB_START anymore. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | | | Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+77
| | | | | | | | | | | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-43/+15
| | | | | | | | | | | | | | | | All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on TQM 85xxKumar Gala2010-01-05-4/+4
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P2020 DSKumar Gala2010-01-05-7/+5
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P1/P2 RDBKumar Gala2010-01-05-6/+4
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on MPC8572 DSKumar Gala2010-01-05-8/+6
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/86xx: Clean up MPC8610 HPCD PCI setup codeKumar Gala2010-01-05-137/+62
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8548 CDS PCI setup codeKumar Gala2010-01-05-93/+48
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up ATUM8548 PCI setup codeKumar Gala2010-01-05-121/+59
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8568 MDS PCI setup codeKumar Gala2010-01-05-92/+45
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8569 MDS PCI setup codeKumar Gala2010-01-05-60/+26
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8544 DS PCI setup codeKumar Gala2010-01-05-179/+70
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8536 DS PCI setup codeMingkai Hu2010-01-05-191/+66
| | | | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | NET: Base support for etsec2.0Kumar Gala2010-01-05-3/+20
| | | | | | | | | | | | | | | | | | | | 1. Modified the tsec_mdio structure to include the new regs 2. Modified the MDIO_BASE_ADDR so that it will handle both older version and new version of etsec. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | NET: Move MDIO regs out of TSEC SpaceSandeep Gopalpet2010-01-05-35/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into platform specific files. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-26 08:50:12 +0000