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* powerpc/85xx: configure autocompletion supportKim Phillips2010-08-01-11/+30
| | | | | | | because it's convenient. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add support for the P4080DS boardKumar Gala2010-08-01-0/+1494
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the P4080DS board, with the following features: * 36-bit only * Boots from NOR flash * FMAN drivers NOT supported * SPD DDR initialization Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Ashish Kalra <Ashish.Kalra@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfigyork2010-07-26-31/+39
| | | | | | | | Enabled SPD Enabled DDR2 Enabled hwconfig Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Improvement to DDR parametersyork2010-07-26-7/+8
| | | | | | Changes for P2020DS DDR applies to other 8xxx platform Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enable DDR3 RDIMM supportyork2010-07-26-53/+72
| | | | | | | | | Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enabled address hashing for 85xxyork2010-07-26-2/+34
| | | | | | | For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enable quad-rank DIMMs.york2010-07-26-21/+61
| | | | | | | Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4york2010-07-26-77/+191
| | | | | | | | | Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enabled hwconfig for memory interleavingKumar Gala2010-07-26-26/+39
| | | | | | | | | | | | | | | | | | | | | Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/p4080: Add workaround for erratum CPU22Kumar Gala2010-07-26-1/+17
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add workaround for errata SERDES8Kumar Gala2010-07-26-0/+295
| | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add support for initializing SERDESKumar Gala2010-07-26-2/+357
| | | | | | | | | | | | | Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support to initialize LIODN registers and portalsKumar Gala2010-07-26-0/+762
| | | | | | | | | | | On the new QorIQ/CoreNet based platforms we need to initialize the "portals" as access into the Data Path subystem as well as Logical IO Device Numbers (LIODN) that are used for the IOMMU (PAMU). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: Add function to alloc phandle valuesKumar Gala2010-07-26-0/+19
| | | | | | | | | | If we are creating reference (handles) to nodes in a device tree we need to first create a new phandle in node and this needs a new phandle value. So we search through the whole dtb to find the max phandle value and return the next greater value for a new phandle allocation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platformsKumar Gala2010-07-26-1/+68
| | | | | | | | | | | | | The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2020: Move INIT_RAM_ADDR physical address higher for 36-bit for P2020DSyork2010-07-26-4/+16
| | | | | | | If 36-bit is enabled, move INIT_RAM_ADDR physical address higher to free lowest 4GB address space. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: Move INIT_RAM_ADDR physical address to 36-bit spaceyork2010-07-26-0/+10
| | | | | | | If 36-bit physical address is used, move the INIT_RAM_ADDR to higher address. This frees the low 4GB address space for better use. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/fsl_fman: Add initial fman immap structuresKumar Gala2010-07-26-0/+213
| | | | | | Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add additional p4080 platform related defines/structsKumar Gala2010-07-26-22/+197
| | | | | | | | | | | | | | | * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fs/fat: Big code cleanup.Wolfgang Denk2010-07-24-755/+697
| | | | | | | | - reformat - throw out macros like FAT_DPRINT and FAT_DPRINT - remove dead code Signed-off-by: Wolfgang Denk <wd@denx.de>
* usb_storage.c: change progress output in debug() messageWolfgang Denk2010-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dots printed by common/usb_storage.c as progress meter corrupt the output for example of "fatls usb" commands like this: => fatls usb 0 . <<==== here 29 file.001 29 file.002 29 file.003 29 file.004 29 file.005 29 file.006 29 file.007 29 file.008 29 file.009 29 file.010 29 file.011 29 file.012 29 file.013 29 file.014 29 file.015 29 file.016 . <<==== here 29 file.017 29 file.018 29 file.019 ... Turn the progress output into a debug message. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
* FAT32: fix broken root directory handling.Wolfgang Denk2010-07-24-10/+50
| | | | | | | | | | | | | | On FAT32, instead of fetching the cluster numbers from the FAT, the code assumed (incorrectly) that the clusters for the root directory were allocated contiguously. In the result, only the first cluster could be accessed. At the typical cluster size of 8 sectors this caused all accesses to files after the first 128 entries to fail - "fatls" would terminate after 128 files (usually displaying a bogus file name, occasionally even crashing the system), and "fatload" would fail to find any files that were not in the first directory cluster. Signed-off-by: Wolfgang Denk <wd@denx.de>
* FAT32: fix support for superfloppy-format (PBR)Wolfgang Denk2010-07-24-4/+10
| | | | | | | | "Superfloppy" format (in U-Boot called PBR) did not work for FAT32 as the file system type string is at a different location. Add support for FAT32. Signed-off-by: Wolfgang Denk <wd@denx.de>
* usb_storage.c: initialize device typeWolfgang Denk2010-07-24-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device type was left uninitialized which caused later tests against DEV_TYPE_UNKNOWN to fail. In the result, "usb part" would attempt to print information about non-existent devices like this: => usb part print_part of 0 Partition Map for USB device 0 -- Partition Type: DOS Partition Start Sector Num Sectors Type 1 0 2031616 f8 print_part of 1 ## Unknown partition table print_part of 2 ## Unknown partition table print_part of 3 ## Unknown partition table print_part of 4 ## Unknown partition table => By initializing the type as DEV_TYPE_UNKNOWN we avoid all the "Unknown partition table" messages. [Note: the "print_part of ?" messages is left over debug code that will be removed in another patch.] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
* cmd_usage(): simplify return code handlingWolfgang Denk2010-07-24-833/+454
| | | | | | | | | | | | | | | | Lots of code use this construct: cmd_usage(cmdtp); return 1; Change cmd_usage() let it return 1 - then we can replace all these ocurrances by return cmd_usage(cmdtp); This fixes a few places with incorrect return code handling, too. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-07-24-0/+62
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| * Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2010-07-24-0/+62
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| | * i2c: soft_i2c: add simple GPIO implementationMike Frysinger2010-07-22-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the vast majority of GPIO I2C implementations behave the same way, support the common GPIO framework with default settings. This adds two new defines CONFIG_SOFT_I2C_GPIO_{SCL,SDA} so that boards which want GPIO I2C support need only define these. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-07-24-451/+1129
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| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-24-33/+440
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| | * | ppc4xx: Enable "ecctest" command on t3corpStefan Roese2010-07-23-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Enable "ecctest" command on katmaiStefan Roese2010-07-23-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 coreStefan Roese2010-07-23-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add "ecctest" command to test/simulate ECC errorsStefan Roese2010-07-23-0/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: DDR/ECC: Use correct macros to clear error statusStefan Roese2010-07-23-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Only define DDR2 registers for the correct PowerPC variantsStefan Roese2010-07-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC valuesStefan Roese2010-07-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: T3CORP fixes and updatesStefan Roese2010-07-23-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 .................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx/Canyonlands added USB board callbacksRupjyoti Sarmah2010-07-23-9/+63
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | powerpc/85xx: Rework P1022 SERDES is_serdes_configured supportKumar Gala2010-07-21-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured supportKumar Gala2010-07-21-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p3041: Add various p3041 related definesKumar Gala2010-07-20-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p3041 to cpu_type_list and SVR list * Added number of LAWs for p3041 * Set CONFIG_MAX_CPUS to 4 for p3041 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p5020: Add various p5020 related defines (and p5010)Kumar Gala2010-07-20-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p5020 & p5010 to cpu_type_list and SVR list * Added number of LAWs for p5020 * Set CONFIG_MAX_CPUS to 2 for p5020 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc85xx: Report FMAN # to match user manualEmil Medve2010-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | The user manual refers to FMAN1 and FMAN2 not 0 and 1. Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p4080: Add setting of clock-frequency for clockgen nodeKumar Gala2010-07-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | On QorIQ CoreNet based devices we have a global clocking block. We want to keep track of SYSCLK frequency as it is what is used to derive all other frequencies in the SoC Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updatesKumar Gala2010-07-20-8/+11
| | | | | | | | | | | | | | | | | | | | | Move to using fdt_node_offset_by_compat_reg to find the node offsets we want to update instead of using aliases. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-162/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fdt: Add fdt_node_offset_by_compat_reg helperKumar Gala2010-07-20-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a compatible string and physical address try and find a node that matches. This is useful when we want to find a specific device node to update (for example if we have multiple PCI nodes we can use the physical address to distinguish them when trying to update the device tree). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | fdt: Add fdt_translate_address to convert reg node to cpu phys addrKumar Gala2010-07-20-0/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is extracted out of the Linux Kernel code from arch/powerpc/kernel/prom_parse.c. We maintain some of the same structure to support multiple bus types even though we only have one in the current code. In the future we might want to translate across a PCI bus and thus it will be easier to add that functionality back in. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641Kumar Gala2010-07-20-138/+136
| | | | | | | | | | | | | | | | | | | | | | | | The MPC8641 boards actually only have PCIE not PCI. Rename so we are uniform with regards to names so we can replace this code with templated code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-05 02:38:43 +0000