| Commit message (Collapse) | Author | Age | Lines |
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
|
|
| |
This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
|
|
|
| |
This update brings the ALPR board support to the newest version.
It also fixes a problem with the NAND driver.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Here the description from Brian Brelsford <Brian_Brelsford@dell.com>:
The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part
returns a 0x15. In the code fragment below bits [1:0] determine the
page size, it is ANDed via "(extid & 0x3)" then shifted out. The
next field is also ANDed with 0x3. However this is a one bit field
as defined in the Hynix and Samsung parts in the 4th ID byte that
determins the oobsize, not a two bit field. It works on Samsung as
bits[3:2] are 01. However for the Hynix there is a 11 in these two
bits, so the oob size gets messed up.
I checked the correct linux code and the suggested fix from Brian is
also available in the linux nand mtd driver.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|\ |
|
| |\ |
|
| | |
| | |
| | |
| | |
| | |
| | | |
- fix a typo in V38B config file
- move watchdog initialisation earlier in the boot process
- add "wdt=off" to default kernel command line (disables kernel watchdog)
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|/ /
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| | |
|
| | |
|
|\ \ |
|
| | |
| | |
| | |
| | | |
offset to go into CFI mode)
|
|\ \ \
| |/ /
|/| | |
|
| | |
| | |
| | |
| | | |
Signed-off-by: Heiko Schocher <hs@denx.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Now 32MByte and 64MByte FLASH is know to work and other
configurations should work too.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
|\ \ \ |
|
| | | |
| | | |
| | | |
| | | | |
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | |
| | | |
| | | |
| | | | |
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| |\ \ \ |
|
| | | | |
| | | | |
| | | | |
| | | | | |
Dave for mpc8360emds, and me for mpc8349emds.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
since they are passed by reference to ucc_get_cmxucr_reg and assigned.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Implement various code style fixes and similar changes.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | | |
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
STDOUT_PATH configuration bits to mpc8349emds,
mpc8349itx, and mpc8360emds board code.
redo environment to use bootm with the fdtaddr
for booting ARCH=powerpc kernels by default,
and provide default fdtaddr values.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Update 83xx OF code to update local-mac-address properties
for ethernet instead of the obsolete 'address' property.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
MPC8360EMDS
This patch also adds an improved I2C set_speed(), which handles all clock
frequencies.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | | |
add doc/README.mpc8360emds to accompany the new board support
|
| | | | |
| | | | |
| | | | |
| | | | | |
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Add support for the Freescale MPC8360EMDS board.
Includes DDR, DUART, Local Bus, PCI.
|
| | | | |
| | | | |
| | | | |
| | | | | |
common QE immap file. Also required for 8360.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Mainly add QE device dependencies, with appropriate 8360 protection.
Lindent also run.
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2"
2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2"
CHANGELOG:
* For the 8349E-mITX, fix some size values in pci_init_board(), enable
the clock for the 2nd USB board (Linux kernel will hang otherwise),
and fix the CONFIG_BOOTARGS macro.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Hello,
Here is a patch for a file that was accidentally left out of a previous
attempt.
It accompanies the patch with ticket DNX#2006090742000024
CHANGELOG:
Change PCI initialization to use new multi-bus I2C API.
regards,
Ben
|