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* fdt_resize(): fix actualsize calculations with unaligned blobsPeter Korsgaard2009-01-17-1/+1
| | | | | | | | | | | | | The code in fdt_resize() to extend the fdt size to end on a page boundary is wrong for fdt's not located at an address aligned on a page boundary. What's even worse, the code would make actualsize shrink rather than grow if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), causing fdt_add_mem_rsv to fail. Fix it by aligning end address (blob + size) to a page boundary instead. For aligned fdt's this is equivalent to what we had before. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
* ncb: use socklen_tMike Frysinger2009-01-16-1/+1
| | | | | | The recvfrom() function takes a socklen_t, not an int. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-01-16-1083/+657
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| * sh: serial: use readx/writex accessorsJean-Christophe PLAGNIOL-VILLARD2009-01-16-23/+23
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: serial: coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-17/+18
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Fix compile error on lowlevel_init fileNobuhiro Iwamatsu2009-01-16-8/+13
| | | | | | | | | | | | | | | | lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Fix up rsk7203 target for out of tree buildKieran Bingham2009-01-16-10/+19
| | | | | | | | | | | | | | Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD2009-01-16-785/+338
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: lowlevel_init coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-634/+640
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: update sh2/sh2a timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-2/+2
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: update sh timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-13/+13
| | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-01-16-163/+184
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| * ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boardsMatthias Fuchs2009-01-14-0/+6
| | | | | | | | | | | | | | | | This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Disable pci node in device tree on CPCI405 pci adaptersMatthias Fuchs2009-01-14-0/+24
| | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Cleanup CPCI405 board codeMatthias Fuchs2009-01-14-163/+144
| | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up CPCI405 board support: - wrap long lines - unification of spaces in function calls - remove dead code Use correct io accessors on peripherals. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable auto RS485 mode on PLU405 boardsMatthias Fuchs2009-01-14-0/+10
| | | | | | | | | | | | | | | | | | | | This patch turns on the auto RS485 mode in the 2nd external uart on PLU405 boards. This is a special mode of the used Exar XR16C2850 uart. Because these boards only have a 485 physical layer connected it's a good idea to turn it on by default. Signed-off-by: Matthias Fuchs <mf@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | Prepare 2009.01-rc2v2009.01-rc2Wolfgang Denk2009-01-14-0/+588
| | | | | | | | | | | | Update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | cpu/mpc824x/Makefile: fix warning with parallel buildsWolfgang Denk2009-01-14-1/+1
|/ | | | | | | | | | Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-14-55/+67
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-14-13/+19
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| | * Some changes of TLB entry setting for MPC8572DSHaiying Wang2009-01-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | | | | | | | | | | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Change PCIE1&2 deciide logic on MPC8544DS board more readableRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bitRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * Fix IO port selection issue on MPC8544DS and MPC8572DS boardsRoy Zang2009-01-13-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | mpc8610hpcd: Fix PCI mapping conceptsBecky Bruce2009-01-13-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
| * | sbc8641d: Fix PCI mapping conceptsBecky Bruce2009-01-13-23/+27
| |/ | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* | MPC86xx: fix build warningsWolfgang Denk2009-01-12-3/+1
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-01-10-61/+93
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| * bf537-stamp/nand: fix board_nand_init prototypeMike Frysinger2009-01-07-1/+3
| | | | | | | | | | | | The board_nand_init() function should return an int, not void. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop CONFIG_SPI handling in board initMike Frysinger2009-01-07-7/+0
| | | | | | | | | | | | | | The eeprom SPI init functions are duplicated as the common code already executes these for us. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix out-of-tree building with ldscriptsMike Frysinger2009-01-07-16/+20
| | | | | | | | | | | | | | Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix linker scripts to work with --gc-sectionsMike Frysinger2009-01-07-36/+48
| | | | | | | | | | | | | | Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: set proper LDRFLAGS for parallel booting LDRsMike Frysinger2009-01-07-1/+22
| | | | | | | | | | | | | | In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | at91rm9200: move define from lowlevel_init to headerJean-Christophe PLAGNIOL-VILLARD2009-01-06-48/+49
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | m501sk: move to the common memory setupJean-Christophe PLAGNIOL-VILLARD2009-01-06-202/+33
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD2009-01-06-203/+203
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | at91: add at91sam9xeek board supportNicolas Ferre2009-01-06-1/+18
| | | | | | | | | | | | | | | | | | | | | | At91sam9xe is basically an at91sam9260 with embedded flash. We can manage it as another entry for at91sam9260 in the Makefile. Check documentation at : http://www.atmel.com/dyn/products/product_card.asp?part_id=4263 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | fix bmp_logo.h make dependencies to allow parallel buildJean-Christophe PLAGNIOL-VILLARD2009-01-06-1/+1
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | at91: Fix Atmel's at91sam9 boards out of tree buildJean-Christophe PLAGNIOL-VILLARD2009-01-06-0/+4
|/ | | | | | introduced in commit 89a7a87f084c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-12-30-83/+3668
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| * 85xx: Enable inbound PCI config cycles for X-ES boards cleanupPeter Tyser2008-12-29-0/+4
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * XPedite5200 board support cleanupPeter Tyser2008-12-29-3/+1200
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-44/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * mpc86xx: Double local bus clock dividerTrent Piepho2008-12-19-0/+1
| | | | | | | | | | | | | | | | The local bus clock divider should be doubled for both 8610 and 8641. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * mpc8568: Double local bus clock dividerTrent Piepho2008-12-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * sbc8548: use proper PHY addressPaul Gortmaker2008-12-19-2/+2
| | | | | | | | | | | | | | | | | | The values given for the PHY address were wrong, so the code read no valid PHY ID, and fell through to the generic PHY support, which would work on 1000M but would not auto negotiate down to 100M or 10M. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * sbc8548: enable command line editing by default.Paul Gortmaker2008-12-19-0/+1
| | | | | | | | | | | | Lets make things a bit more user friendly. It isn't 1985 anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * sbc8548: don't enable the 3rd and 4th eTSECPaul Gortmaker2008-12-19-14/+1
| | | | | | | | | | | | | | These interfaces don't have usable connectors on the board, so don't bother enumerating or configuring them. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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