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* ppc4xx: Remove CONFIG_SYS_IGNORE_405_UART_ERRATA_59 from config filesMatthias Fuchs2009-01-26-24/+0
| | | | | | | | | Lot's of 405 board config files use CONFIG_SYS_IGNORE_405_UART_ERRATA_59. Either they define or undef it. Because it's not used in any source files this patch removes any references to it. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add GDsys PowerPC 440 ETX board support.Dirk Eibach2009-01-26-0/+838
| | | | | | | | Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Improve DDR autodetectDirk Eibach2009-01-26-5/+50
| | | | | | | | | Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-24-232/+595
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| * 85xx: Add a 36-bit physical configuration for MPC8572DSKumar Gala2009-01-23-2/+54
| | | | | | | | | | | | | | We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Handle eLBC difference w/36-bit physicalKumar Gala2009-01-23-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Use BR_ADDR macro for NAND chipselectsKumar Gala2009-01-23-8/+8
| | | | | | | | | | | | | | | | | | Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-9/+29
| | | | | | | | | | | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * 85xx: enable the auto self refresh for wake up ARPDave Liu2009-01-23-0/+6
| | | | | | | | | | | | | | | | The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+21
| | | | | | | | | | | | | | | | | | For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+16
| | | | | | | | | | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | | | | According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala2009-01-23-8/+30
| | | | | | | | | | | | | | | | | | Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala2009-01-23-54/+84
| | | | | | | | | | | | | | | | | | Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boardsKumar Gala2009-01-23-9/+10
| | | | | | | | | | | | | | | | Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-47/+55
| | | | | | | | | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-95/+103
| | | | | | | | | | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx: separate FLASH BASE virtual from physical addressKumar Gala2009-01-23-14/+16
| | | | | | | | | | | | | | | | | | | | Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx: separate PIXIS virtual from physical addressKumar Gala2009-01-23-6/+8
| | | | | | | | | | | | | | | | | | | | Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
| * Add README file for MPC8572DS boardHaiying Wang2009-01-23-0/+167
| | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-01-24-76/+1924
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| * \ Merge branch 'next'Kim Phillips2009-01-23-202/+2883
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| | * mpc83xx: New board support for SIMPC8313Ron Madrid2009-01-23-0/+1186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * 83xx: Use the proper sequence for updating IMMR.Scott Wood2009-01-21-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov2009-01-21-5/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Add PCI-E support for MPC8315ERDB boardsAnton Vorontsov2009-01-21-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Add support for MPC83xx PCI-E controllersAnton Vorontsov2009-01-21-23/+488
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent modeIra Snyder2009-01-21-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do not enable them. See the MPC8349EA Reference Manual, Section 4.4.2 "Clocking in PCI Agent Mode". Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * 83xx: PCI agent mode fixes for multi-board systemsIra Snyder2009-01-21-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, the boards will lock up the PCI bus by scanning against each other. The boards lock against each other by trying to access the PCI bus before clearing their configuration lock bit. Both boards end up in a loop, sending and receiving "Target Not Ready" messages forever. When running in PCI agent mode, the scanning now takes place after the boards have cleared their configuration lock bit. Also, add a missing declaration to the mpc83xx.h header file, fixing a build warning. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Size optimization of start.SRon Madrid2009-01-21-38/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * Merge branch 'master' into nextKim Phillips2009-01-21-5566/+27040
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| | * | powerpc, keymile boards: extract identical config optionsHeiko Schocher2008-11-24-216/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extracts the identical config options for the keymile boards mgcoge, mgsuvd and kmeter1 in a new common config file keymile-common.h. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | powerpc: keymile: Add a check for the PIGGY debug boardHeiko Schocher2008-11-24-10/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the presence of the PIGGY on the keymile boards mgcoge, mgsuvd and kmeter1. If the PIGGY is not present, dont register this Ethernet device. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | powerpc: 83xx: add support for the kmeter1 boardHeiko Schocher2008-11-20-0/+847
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | | easylogo: add optional gzip supportMike Frysinger2009-01-24-6/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some images can be quite large, so add an option to compress the image data with gzip in the U-Boot image. Then at runtime, the board can decompress it with the normal zlib functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | | fat: fix unaligned errorsBryan Wu2009-01-24-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of buffers in the fat code are declared as an array of bytes. But it is then cast up to a structure with 16bit and 32bit members. Since GCC assumes structure alignment here, we have to force the buffers to be aligned according to the structure usage. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | | spi flash: fix crash due to spi flash miscommunicationBrad Bozarth2009-01-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Higher spi flash layers expect to be given back a pointer that was malloced so that it can free the result, but the lower layers return a pointer that is in the middle of the malloced memory. Reorder the members of the lower spi structures so that things work out. Signed-off-by: Brad Bozarth <bflinux@yumbrad.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | | | FPU POST: fix warnings when building with 2.18 binutilsYuri Tikhonov2009-01-24-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compile u-boot with the 2.18 binutils the following warning messages for each object file in post/lib_ppc/fpu/ is produced at the linking stage: post/libpost.a(acc1.o) uses hard float, u-boot uses soft-float ... This is because of the fact that, in general, the soft-float and hard-float ABIs are incompatible; the 2.18 binutils do checking of the Tag_GNU_Power_ABI_FP attribute of the files to be linked, and produce the worning like above if these are not compatible. The incompatibility of ABIs is concerned only the float values: e.g. the soft-float ABI assumes the float argument passing in the pair of rX registers, and the hard-float ABI assumes passing of the float argument in the fX register. When we don't pass the float arguments between the functions compiled with different floatness, then such an application will work correctly. This is the case for the FPU POST: u-boot (compiled with soft-float) doesn't pass to (and doesn't get from) the FPU POST functions any floats; there are no functions exported from the post/lib_ppc/fpu/ objects which would work with float parameters/returns too. So, we can reassure the linker not to worry about the difference in ABI attributes of linking files just by setting the 'soft-float' attribute for the objects in post/lib_ppc/fpu. And this patch does this. Also, to avoid passing both soft- and hard-float options in CFLAGS when compiling the files from post/lib_ppc/fpu (which is OK, but looks rather dirty) this patch removes the soft-float string from CFLAGS in post/lib_ppc/fpu/Makefile. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | | | Add support for Maxim's DS4510 I2C devicePeter Tyser2009-01-24-0/+504
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial support for the DS4510, a CPU supervisor with integrated EEPROM, SRAM, and 4 programmable non-volatile GPIO pins. The CONFIG_DS4510 define enables support for the device while the CONFIG_CMD_DS4510 define enables the ds4510 command. The additional CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and CONFIG_DS4510_RST defines add additional sub-commands to the ds4510 command when defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | | | common: Iteration limit for memory test.Dirk Eibach2009-01-24-14/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iteration limit is passed to mtest as a fourth parameter: [start [end [pattern [iterations]]]] If no fourth parameter is supplied, there is no iteration limit and the test will loop forever. Signed-off-by: Dirk Eibach <eibach@gdsys.de>
* | | | serial: Rename driver vcth to vct to support other board variantsStefan Roese2009-01-24-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved driver vcth.c to vct.c to better reflect the VCT board series. This driver is now used by the VCT platforms: vct_premium vct_platinum vct_platinumsvc Signed-off-by: Stefan Roese <sr@denx.de>
* | | | nios: Move README.nios_CONFIG_SYS_NIOS_CPU to doc/ dirShinya Kuribayashi2009-01-24-0/+0
| | | | | | | | | | | | | | | | Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | | | common/main: support bootdelay=0 for CONFIG_AUTOBOOT_KEYEDPeter Korsgaard2009-01-24-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the !CONFIG_AUTOBOOT_KEYED case. Do this by reversing the loop so we do at least one iteration before checking for timeout. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
* | | | Added legacy flash ST Micro M29W040BNiklaus Giger2009-01-24-0/+14
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* | | | Fixed off-by-one errors in lib_m68k/interrupts.cGraeme Russ2009-01-24-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | | Removed all references to CONFIG_SYS_RESET_GENERICGraeme Russ2009-01-24-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Generic i386 reset - #define made redundant by weak function Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | | Remove #ifdef CONFIG_SC520 in source codeGraeme Russ2009-01-24-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SC520 is now used for conditional compile Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | | Added MMCR reset functionalityGraeme Russ2009-01-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset function specific to AMD SC520 microcontroller - Is more of a 'hard reset' that the triple fault. Requires CONFIG_SYS_RESET_SC520 to be defined in config I would have liked to add this to a new file (cpu/i386/sc520/reset.c) but ld requires that a object file in a library arhive MUST contain at least one function which does not override a weak function (and is called from outside the object file) in order for that object file to be extracted from the archive. This would be the only function on the new file, and hence, will never get linked in. Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | | Moved generic (triple fault) reset codeGraeme Russ2009-01-24-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved from interrupts.c to cpu.c and made into a weak function to allow vendor specific override Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be added to the vendor specific code without the need to remember to #undef usage of the generic method and if you forget to include your custom reset method, you will always get the default. Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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