| Commit message (Collapse) | Author | Age | Lines |
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This patch moves the PPC4xx specific I2C device driver into the I2C
drivers directory. All 4xx config headers are updated to include this
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
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pci_eth_init() is already conditional to CONFIG_PCI so not every caller
needs to have conditionals.
This is the only place in the current code base where such a check is
still at the calling site.
Signed-off-by: Detlev Zundel <dzu@denx.de>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Peter Pearse <peter.pearse@arm.com>
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This patch is part of migrating the AT91 support towards
using C struct for all SOC access.
It removes one more CONFIG_AT91_LEGACY warning.
at91_pmc.h needs cleanup after migration of the drivers
has been done.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
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Signed-off-by: Asen Dimov <dimov@ronetix.at>
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Previous code was failing when reading back the timer less than
400us after resetting it. This lead nand operations to incorrectly
timeout any now and then. Moreover, writing the load register isn't
immediately reflected in the value register. We must wait for a clock
edge, so read_timer now waits for the value to change at least once,
otherwise nand operation would timeout anyways (though less frequently).
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
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This converts the at91 watchdog driver to new c structure
type to access registers of the SoC
Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
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CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing
This clean up patch removes the references for esd boards
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
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ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and
performing (almost) all manipulation of the timer structure in read_timer()
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
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ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to
'timer_regs' in order to avoid confusion with the global variable 'timer'
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
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Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
loaded over tftp.
The preinit function will configure GPIO (GPK0CON) & SROMC to look
for environment in SROM Bank 3.
Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Nand Flash, Ethernet, other features might need to configure the
SROMC registers accordingly.
The config_sromc() functions helps with this.
Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
smc.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.
Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Because adds support the GPIO Interface, README file is updated.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds support the GPIO interface
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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The s3c6400.h file is only for S3C64XX cpu and the pheripheral port
address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they
should be included by only S3C64XX cpu.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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The get_pll_clk(int) API returns the PLL frequency based on
the (int) argument which is defined locally in clock.c
Moving that #define to common header file (clk.h) would
be helpful when using the API from other files.
Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
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When the timestamp is incremented via interrupt and the interrupt
period is greater than 1 msec, successive calls to get_timer() can
produce inaccurate timing since the interrupts are asynchronous
to the timing loop. For example, with an interrupt period of 10 msec
two successive calls to get_timer() could indicate an elapsed time
of 10 msec after only several hundred usecs -- depending on when
the next interrupt actually occurs. This behavior can cause
reliability issues with components such as CFI and NAND.
This can be remedied by calling reset_timer() prior to establishing
the base timestamp with get_timer(0), provided reset_timer()
resets the hardware timer (rather than simply resetting only the
timestamp). This has the effect of synchronizing the interrupts
(and the advance of the timestamp) with the timing loop.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This patch adds bootargs passing to nios2 linux.
The args passing is enabled with,
r4 : 'NIOS' magic
r5 : pointer to initrd start
r6 : pointer to initrd end
r7 : pointer to command line
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration
headers. Updated comments to accurately describe timebase macros.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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The outx/writex macros were using writex(addr, val) rather than
the standard writex(val, addr), resulting in incompatibilty with
architecture independent components. This change set uses standard
parameter order.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This is needed for jffs2 support.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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These are needed to use ubi/ubifs.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Copy from linux header. This is needed for generic bitops.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Just pull in asm-generic.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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The standard Altera UART & JTAG UART as well as the OpenCores
YANU driver are now in individual files in drivers/serial
rather than a single file uner cpu/nios2.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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and removed it from the .h file
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
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The code to parse alen appeared 6 times in the function.
Factored this out in a small helper function
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
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Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
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Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
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Declared all functions that were not called outside the file as static
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
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This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.
This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.
This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
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The ATMEL flash does not have buffer write feature. Assgined
buffer_size = 1, so that when there is a write to the flash
will not use buffer write function.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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The flash location is at 0xff800000, not 0
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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The CF will call cache functions in lib_m68/cache.c and the
cache settings are defined in platform configuration file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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The proper SDRAM size is 32MB not 64MB
Signed-off-by: Jingchang Lu <b22599@freescale.com>
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Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add
CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update
DRAM control and SRAM control register setting. Update cache
setting where size does not write to proper region.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add CPU compile flag -mcpu=53015 in cpu/config.mk
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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Provide extra environment Data. Remove default network
address and MAC address.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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Fix proper portsize: The register for portsize is either 00b, 01b,
or 1xb. The value that previous assigned is 32d.
Fix DRAM bring up: insert asm("nop") for every DRAM register setup
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
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