| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
| |
This bug was detected on the LWMON5 target which has 2 Intel 16bit wide
flash chips connected to a 32bit wide port.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
|
|
|
|
|
| |
The check for an sufficiently erased destination was missing in the
buffered write function of the cfi flash driver (when
CFG_FLASH_USE_BUFFER_WRITE is defined). This patch adds this check to that
writing to such a region will fail with the currect error message.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| | |
- enable command line history
- increase malloc space (because of bigger flash sectors)
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| | |
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| | |
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| |
| |
| |
| |
| | |
CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
On the TQM885D the measurement of cpuclk with the PIT reference
timer ist not necessary. Since all module variants use the same
external 10 MHz oscillator, the cpuclk only depends on the PLL
configuration - which is readable by software.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 128. This result
in a refresh rate of 4 * 7.8 us at the default clock
66 MHz. At 133 MHz the value will be then 4 * 3.8 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| | |
Signed-off-by: Martin Krause <martin.krause@tqs.de>
|
| |
| |
| |
| | |
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|\ \
| |/ |
|
| |\
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Conflicts:
MAINTAINERS
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The composition of the directory in the drivers/ changed.
I moved SuperH serial driver and marubun PCMCIA driver.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | |\ |
|
| | |\ \
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Conflicts:
drivers/Makefile
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
This document is a summary of information concerning SuperH of U-Boot.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Marubun pcmcia is a chip for PCMCIA used with SuperH.
Of course, this can be used even by other architectures.
When use this driver, came to be able to use CompactFlash
and Ethernet.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
- Changed volatile unsigned to vu_.
- Changed Makefile for kconfig.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | |\ \ \
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Conflicts:
drivers/Makefile
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Add support MS7722SE01 to Makefile.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | |\ \ \ \
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Conflicts:
CREDITS
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
This adds support for the Hitachi MS7750SE.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|\ \ \ \ \ \ \
| |/ / / / / / |
|
| |\ \ \ \ \ \ |
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
disable_interrupts() should return nonzero if interrupts were
_enabled_ before, not disabled.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
The timer code depends on the timer interrupt to keep track of the
upper 32 bits of the cycle counter. This obviously doesn't work when
interrupts are disabled the whole time.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
As reported by Gerhard Berghofer:
in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
instead of PB18 and PB19.
which is obviously correct. There's currently no code that uses
USART3, but custom boards may run into problems.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
As noted by Kim Phillips, these lists tend to become out of date.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
Add all the ATSTK1000 daughterboards to MAINTAINERS along with their
"mother". Also update the entry for ATSTK1000 to be not only about the
AP7000 CPU; it's intended to handle all CPUs in the AT32AP family.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
Add a chip-features file providing definitions of the form
AT32AP700x_CHIP_HAS_<peripheral>
to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| | | |_|_|_|/
| | |/| | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Show controller status as well as card status when an error occurs
during block read.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
|\ \ \ \ \ \ \
| |/ / / / / /
|/| | | | | | |
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
* Enabled CONFIG_CMD_ELF
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
* Removed some misc environment setup
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Minor path corrections needed to ensure buildability.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|