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* POST: Fix merge problemStefan Roese2007-08-14-4/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanupStefan Roese2007-08-14-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-43/+4149
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| * ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-44/+1344
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * POST: Add option for external ethernet loopback testStefan Roese2007-08-14-1/+8
| | | | | | | | | | | | | | | | When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST is not done using an internal loopback connection, but by assuming that an external loopback connector is plugged into the board. Signed-off-by: Stefan Roese <sr@denx.de>
| * POST: Add ppc405 support to cache and UART POSTStefan Roese2007-08-14-7/+186
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken2007-07-26-6/+2622
| | | | | | | | Signed-off-by: John Otken <john@softadvances.com>
* | ppc4xx: Fix problem in PLL clock calculationStefan Roese2007-08-13-18/+26
| | | | | | | | | | | | | | This patch was originall provided by David Mitchell <dmitchell@amcc.com> and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese <sr@denx.de>
* | Coding style cleanupStefan Roese2007-08-10-152/+153
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Add PPC4xx-HCU4 and HCU5 boards: HCU5 filesNiklaus Giger2007-08-10-0/+906
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: HCU4 filesNiklaus Giger2007-08-10-0/+393
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: common filesNiklaus Giger2007-08-10-0/+570
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: make relatedNiklaus Giger2007-08-10-0/+448
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: HCU5 configNiklaus Giger2007-08-10-0/+392
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: HCU4 configNiklaus Giger2007-08-10-0/+343
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: READMEsNiklaus Giger2007-08-10-0/+233
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | Add PPC4xx-HCU4 and HCU5 boards: InfrastructureNiklaus Giger2007-08-10-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series of patches adds support for 2 boards from Netstal Maschinen. The HCU4 has a PPC405Gpr and the HCU5 has a PPC440EPX. The HCU4 has a somehow complicated flash setup, as the booteprom is only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more elegant solution. The HCU5 has only a booteprom as the whole code will be downloaded from a different board which has HD, CD-ROM, etc and where all code is stored. This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. Thanks them a lot. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | ppc4xx: Update lwmon5 POST configurationStefan Roese2007-08-10-2/+19
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | POST: Add ppc4xx UART POST support without external uart clock (lwmon5)Yuri Tikhonov2007-08-10-0/+43
| | | | | | | | | | | | | | | | The patch adds support for UART POST on ppc44x-based boards with no external serial clocks installed. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update AMCC Bamboo README doc/README.bambooStefan Roese2007-08-06-0/+62
| | | | | | | | | | | | | | As suggested by Eugene O'Brien <Eugene.O'Brien@advantechamt.com>, here an updated Bamboo README. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-02-1/+7
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| * | Fix breakage of 8xx boards from recent commit.Rafal Jaworowski2007-07-19-1/+7
| | | | | | | | | | | | | | | | | | | | | This patch fixes the negative consequences for 8xx of the recent "ppc4xx: Clean up 440 exceptions handling" commit. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* | | ppc4xx: Code cleanupStefan Roese2007-08-02-1/+1
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [ppc440SPe] Graceful recovery from machine check during PCIe configurationGrzegorz Bernacki2007-08-02-10/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
* | | [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.ARafal Jaworowski2007-08-02-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* | | ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien2007-07-31-110/+248
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update 440EPx lwmon5 board supportStefan Roese2007-07-31-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Only print ECC related info when the error bis are setStefan Roese2007-07-30-14/+24
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | new FPGA image for PLU405 boardMatthias Fuchs2007-07-28-1160/+1179
| | | | | | | | | | | | | | | | | | new FPGA image for PLU405 board with improved CompactFlash timing Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | ppc4xx: lwmon5: Update Lime initializationAnatolij Gustschin2007-07-26-5/+73
| |/ |/| | | | | | | | | | | | | | | Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: lwmon5: Support for 128 MByte NOR FLASH addedStefan Roese2007-07-24-6/+8
| | | | | | | | | | | | | | The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)Stefan Roese2007-07-24-6/+6
| | | | | | | | | | | | | | As suggested by Hakan Eryigit, here an updated setup for the lwmon5 interrupt controller. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix bug with default GPIO output valueStefan Roese2007-07-20-2/+2
| | | | | | | | | | | | | | As spotted by Matthias Fuchs, the default output values for all GPIO1 outputs were not setup correctly. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
* | POST: Add ECC POST for the lwmon5 boardPavel Kolesnikov2007-07-20-1/+318
| | | | | | | | | | | | | | | | | | This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-07-16-307/+1836
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| * Update CHANGELOGWolfgang Denk2007-07-14-0/+31
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/hs/Atronic/u-boot-dev-newHeiko Schocher2007-07-14-279/+188
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| | * make show_boot_progress () weak.Heiko Schocher2007-07-13-276/+173
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * [PCS440EP] - The DIAG LEDs are now blinking, if an error occurHeiko Schocher2007-07-13-4/+16
| | | | | | | | | | | | | | | | | | - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher <hs@denx.de>
| * | [PCS440EP] - fix compile error, if BUILD_DIR is usedHeiko Schocher2007-07-14-1/+1
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| * Update CHANGELOG, minor coding style cleanup.Wolfgang Denk2007-07-12-6/+34
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/tur/git/u-boot#cm1_qp1Wolfgang Denk2007-07-12-13/+1487
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| | * CM1.QP1: Support for the Schindler CM1.QP1 board.Bartlomiej Sieka2007-07-11-13/+1487
| | | | | | | | | | | | | | | Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| * | [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failedHeiko Schocher2007-07-11-14/+101
| | | | | | | | | | | | | | | | | | | | | | | | - now the Flash ST M29W040B is supported (not tested) - fix the "led" command - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ppc4xx: Code cleanupStefan Roese2007-07-16-2/+0
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setupStefan Roese2007-07-16-1/+7
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.cStefan Roese2007-07-16-0/+34
| | | | | | | | | | | | | | | | | | | | | The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese2007-07-16-14/+44
| | | | | | | | | | | | | | | | | | | | | The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Change receive buffer handling in the 4xx emac driverStefan Roese2007-07-12-3/+5
| | | | | | | | | | | | | | | | | | | | | This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese <sr@denx.de>
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