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* i386: Misc PCI fixupsGraeme Russ2009-09-04-11/+14
| | | | | | | | | | | | | | | | | | | | Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in commit ff4e66e93c1a, regressed by commit 6d7f610b09f8) Cast PCI_ROM_ADDRESS_MASK to u32 Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO Change call to pci_find_class() to pci_find_devices(). This is based on a patch submitted on 1st March 2007 (Patch that fixes the compilation errors for sc520_cdp board) by mushtaq_k This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be specified in the board config file. Dummy values have been added for the SC520 CDP board to enable compilation, but since I do not have one of these, I do know what the values should be Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Fix sc520 timer interrupt generationGraeme Russ2009-09-04-3/+3
| | | | | | | | The current implementation has the timer being started before the interrupt handler is installed. It the interrupt occurs before the handler is installed, the timer interrupt is never reset and the timer stops Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Fix environment configuration for eNET boardGraeme Russ2009-09-04-6/+5
| | | | | | | | The current configuration of the Environment has the redundant copy of the environment in the Boot Flash - This was never the intent. The Environment should instead be in the first two sectors of the first Strata Flash Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* i386: Fix regression introduced by commit 8c63d47651f7Graeme Russ2009-09-04-0/+5
| | | | | | A local variable was deleted that should not have been Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* i386: Change inline asm global symbols to localGraeme Russ2009-09-04-4/+4
| | | | | | | | gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why) Remove use of global names for labels to prevent 'symbol already defined' errors Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* i386: Add errno.hGraeme Russ2009-09-04-0/+1
| | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Consolidate arch-specific mem_malloc_init() implementationsPeter Tyser2009-09-04-139/+32
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Standardize mem_malloc_init() implementationPeter Tyser2009-09-04-88/+79
| | | | | | | | | | This lays the groundwork to allow architectures to share a common mem_malloc_init(). Note that the x86 implementation was not modified as it did not fit the mold of all other architectures. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Consolidate arch-specific sbrk() implementationsPeter Tyser2009-09-04-230/+28
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* atmel_df_pow2: standalone to convert dataflashes to pow2Mike Frysinger2009-09-04-0/+214
| | | | | | | | | | | | Atmel DataFlashes by default operate with pages that are slightly bigger than normal binary sizes (i.e. many are 1056 byte pages rather than 1024 bytes). However, they also have a "power of 2" mode where the pages show up with the normal binary size. The latter mode is required in order to boot with a Blackfin processor, so many people wish to convert their DataFlashes on their development systems to this mode. This standalone application does just that. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: cm-bf548: fix device->stdio_dev falloutMike Frysinger2009-09-02-3/+3
| | | | | | | The recent 52cb4d4fb348 commit which renamed device to stdio_dev missed the cm-bf548's video board. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: enable 64bit printf for nandMike Frysinger2009-09-02-0/+3
| | | | | | | | Since the NAND code now uses 64bit code, make sure we enable support for ADI Blackfin boards in printf to avoid the warning: nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use scratch pad for exception stackMike Frysinger2009-09-02-0/+9
| | | | | | | | | If the memory layout pushes the stack out of the default DCPLB coverage, the exception handler may trigger a double fault by trying to push onto the uncovered stack. So handle the exception stack similar to the kernel by using the top of the scratch pad SRAM. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: increase default console sizeMike Frysinger2009-09-02-5/+1
| | | | | | | The default console size indirectly applies to length of env vars, so a smaller length makes it hard to pass longer command lines to kernels. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix debug printf modifiersMike Frysinger2009-09-02-18/+18
| | | | | | | The display_global_data() function generated warnings with pretty much every variable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: cm-bf537u: new board portHarald Krapfenbauer2009-09-02-1/+411
| | | | | | | | The CM-BF537U is similar to the CM-BF537E module, but enough to need its own board port. Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: change global data register from P5 to P3Robin Getz2009-09-02-7/+7
| | | | | | | | | | | Since the Blackfin ABI favors higher scratch registers by default, use the last scratch register (P3) for global data rather than the first (P5). This allows the compiler's register allocator to use higher number scratch P registers, which in turn better matches the Blackfin instruction set, which reduces the size of U-Boot by more than 1024 bytes... Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: enable more network commands for ADI dev boardsRobin Getz2009-09-02-0/+10
| | | | | | | | Add dns and ntp to default networking commands, and ask for more dhcp options to better configure the network environment. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: comment CF-Flash Card Support betterMichael Hennerich2009-09-02-5/+24
| | | | | Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use +(filesize) to make sure we are only doing what is necessaryRobin Getz2009-09-02-2/+2
| | | | | Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'next' of ../nextWolfgang Denk2009-08-31-4436/+5680
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| * fsl: simplify the "mac id" command, improve boot-time informational messageTimur Tabi2009-08-28-32/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "mac id" command took a 4-character parameter as the identifier string. However, for any given board, only one kind of identifier is acceptable, so it makes no sense to ask the user to type it in. Instead, if the user enters "mac id", the identifier (and also the version, if it's NXID) will automatically be set to the correct value. Improve the message that is displayed when EEPROM is read during boot. It now displays "EEPROM:" and then either an error message or the EEPROM identifier if successful. If the identifier in EEPROM is valid, then always reject a bad CRC, even if the CRC field has not been initialized. Don't force the MAC address count to MAX_NUM_PORTS or less. Forcing the value to be changed resulting in an in-memory copy that does not match what's in hardware, even though the user did not request that change. Finally, always update the CRC value in the in-memory copy after any field is changed, so that the CRC is always correct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added PCIe support for P1 P2 RDBPoonam Aggrwal2009-08-28-1/+125
| | | | | | | | | | | | | | Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+70
| | | | | | | | | | | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Improve MPIC initializationTimur Tabi2009-08-28-5/+7
| | | | | | | | | | | | | | | | | | The MPIC initialization code for Freescale e500 CPUs was not using I/O accessors, and it was not issuing a read-back to the MPIC after setting mixed mode. This may be the cause of a spurious interrupt on some systems. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added support for P1011RDB and P2010RDBPoonam Aggrwal2009-08-28-0/+12
| | | | | | | | | | | | | | | | P1011 and P2010 are single core variants of P1010 and P2020 respectively. The board(RDB) will be same. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-6/+17
| | | | | | | | | | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: P1020RDB Support AddedPoonam Aggrwal2009-08-28-0/+6
| | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added CONFIG_MAX_CPUS for P1020Poonam Aggrwal2009-08-28-2/+2
| | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-2/+8
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Fix memory test range on MPC8536DSFelix Radensky2009-08-28-2/+2
| | | | | | | | | | | | | | | | | | | | With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END memory test hangs if run without arguments. Set them to sane values, so that all available 512MB of RAM excluding exception vectors at the bottom and u-boot code and stack at the top can be tested. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Removed BEDBUG support on P1_P2_RDBKumar Gala2009-08-28-1/+0
| | | | | | | | | | | | To match all other 85xx platforms we are removing BEDBUG support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Init pci ethernet cards if we enable any on MPC8572DSKumar Gala2009-08-28-1/+2
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * xes: Use proper IO access functionsPeter Tyser2009-08-28-38/+37
| | | | | | | | | | | | | | Also fix some minor whitespace oddities while we're cleaning up Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Move to a common linker scriptKumar Gala2009-08-28-3349/+3
| | | | | | | | | | | | | | | | There are really no differences between all the 85xx linker scripts so we can just move to a single common one. Board code is still able to override the common one if need be. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-28-1/+1521
| | | | | | | | | | | | | | | | | | | | | | | | | | The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-75/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-100/+135
| | | | | | | | | | | | | | | | Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * stx: create common vendor/board hierarchy for STx boardsAlex Dubov2009-08-28-3/+3
| | | | | | | | | | | | | | | | Move files belonging to the STx boards into common vendor directory and update the Makefile to reflect this. Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Remove unused CONFIG_CLEAR_LAW0 definesPeter Tyser2009-08-28-3/+0
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 86xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 However these are all captured in the config.h and thus redudant. Also moved common 86xx flags into cpu/mpc86xx/config.mk. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-82/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 However these are all captured in the config.h and thus redudant. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add a 36-bit physical configuration for MPC8536DSKumar Gala2009-08-28-11/+76
| | | | | | | | | | | | | | | | | | | | We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Cleanup whitespace in mpc8536ds.cKumar Gala2009-08-28-11/+5
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memoryKumar Gala2009-08-28-63/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala2009-08-28-19/+14
| | | | | | | | | | | | | | | | Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-120/+7
| | | | | | | | | | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-95/+42
| | | | | | | | | | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Merge branch 'next' of git://git.denx.de/u-boot-nand-flash into nextWolfgang Denk2009-08-28-12/+1538
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