| Commit message (Collapse) | Author | Age | Lines |
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Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered.
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
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- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
-- Timer Value Register @ TIMER Base + 4 is Read-only.
-- Prescale Value (Bits 3-2 of TIMER Control register)
can only be one of 00,01,10. 11 is undefined.
-- CFG_HZ for Versatile board is set to
#define CFG_HZ (1000000 / 256)
So Prescale bits is set to indicate
- 8 Stages of Prescale, Clock divided by 256
- The Timer Control Register has one Undefined/Shouldn't Use Bit
So we should do read/modify/write Operation
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
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Signed-off-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
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ARM DaVinci: Removed redundant NAND initialization code.
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
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ARM DaVinci: Fix compilation error with new MTD code.
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
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During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:
- Rework memory-queue and PLB arbiter optimization code, that the
local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
of XXX+ 0x01). This was not introduced by Prodyut, just a
copy-paste problem.
Signed-off-by: Stefan Roese <sr@denx.de>
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PPC405EX and PPC460EX/GT/SX
- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
processors
- Add register bit definitions for Memory Queue Configuration registers
Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Recently the YAFFS filesystem support has been added to U-boot.
However, just enabling CONFIG_YAFFS2 is not enough to get it working.
ymount will generate an exception (when dereferencing mtd->readoob()), because
the genericDevice is a null pointer. Further, a lot of logging is produced
while using YAFFS fs, so logging should also be disabled.
Both issues are solved by this patch.
With this patch and CONFIG_YAFFS2 enabled, I get a readable filesystem
in U-boot, as well as in Linux.
Tested on a Atmel AT91SAM9261EK board.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Acked-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Also sync with kernel OneNAND codes
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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It was for debugging purposes, and shouldn't have been left in.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.
This makes the code a bit more flexible to the number of ethernet
interfaces.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch changes the debug_printf() marco for U-Boot in hush.c and
moves the definition of DEBUG_SHELL to a place that is actually compiled
under U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
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Commit 00b1883a4cac59d97cd297b1a3a398db85982865
missed a few boards:
include/configs/M5253DEMO.h
include/configs/ml507.h
include/configs/redwood.h
This patch fixes this.
Signed-off-by: Heiko Schocher <hs@denx.de>
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ARM, i386, m68k and ppc all have identical implementations of strmhz().
Other architectures don't provide this function at all.
This patch moves strmhz() into lib_generic, reducing code duplication
and providing a more unified API across architectures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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fix build warnings @ mvBC-P board by using correct types, i.e. change
out_be32 to out_be16 and out_8 accordingly.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Tested with TQM5200S on STK52XX.200 Board
Signed-off-by: Axel Beierlein <belatronix@web.de>
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The last used chip, address, and address length were not being
stored for the imm and imn commands.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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Correct a small spelling mistake.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
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This patch adds a hook whereby a board-specific routine can be called to
configure hardware for a PIO mode. The prototype for the board-specific
routine is:
int inline ide_set_piomode(int pio_mode)
ide_set_piomode should be prepared to configure hardware for a pio_mode
between 0 and 6, inclusive. It should return 0 on success or 1 on failure.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
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This patch removes some enums from ata.h and replaces them with an
include of libata.h. This way, we eliminate duplicated code, and
prevent errors whereby the different versions could be out of sync.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
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rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch fixes a missing vendor code in the flash_real_protect() function.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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New implement sector lock and unlock or softlock commands
do not exist in AMD legacy flash. Thus, causing issue
when erasing AMD legacy flash (such as lv040)
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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CFG_FLASH_CFI_DRIVER was recently renamed CONFIG_FLASH_CFI_DRIVER.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Conflicts:
MAINTAINERS
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Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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The rest of the MAINTAINERS file appears to be sorted
almost-alphabetically, but entries for the newly added AVR32 boards were
added somewhat randomly. This patch sorts the list alphabetically again.
Also update my e-mail address. The old one still works, but it may not
work forever.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Conflicts:
MAKEALL
Makefile
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The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra
8MByte FLASH and 128KByte FRAM.
Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Conflicts:
MAINTAINERS
MAKEALL
Makefile
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This patch adds support for the Favr-32 board made by EarthLCD.
This kit, which is also called ezLCD-101 when running with EarthLCD firmware,
has a 10.4" touch screen LCD panel, 16 MB 32-bit SDRAM, 8 MB parallel flash,
Ethernet, audio out, USB device, SD-card slot, USART and various other
connectors for cennecting stuff to SPI, I2C, GPIO, etc.
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Renamed initialization functions for atngw100 and atstk1000.
Removed initializations for these boards from net/eth.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This patch fixes a problem that RTL8110SCL started transfer
with an incorrect memory address.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The received status and len was in little endian
format and caused the ethernet unable to proceed
further. Add __le16_to_cpu() in dm9000_rx_status_8/16/32bit().
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache. All callers of invalidate_l1_instruction_cache()
call icache_disable() right after. Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.
Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The ePAPR spec has some subtle differences from the current device
tree based boot interface to the powerpc linux kernel. The powerpc
linux kernel currently ignores the differences that ePAPR specifies.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
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