summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* smc911x_eeprom: fix building after smc911x overhaulMike Frysinger2009-11-12-60/+62
| | | | | | | | | | When the smc911x driver was converted to NET_MULTI, the smc911x eeprom was missed. The config option needed updating as well as overhauling of the rergister read/write functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-11-11-36/+44
|\
| * mxc_fec: avoid free() calls to already freed pointers.javier Martin2009-11-11-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes, inside NetLoop, eth_halt() is called before eth_init() has been called. This is harmless except for free() calls to pointers which have not been allocated yet. This patch initializes those pointers to NULL and allocates them only the first time. This way we can get rid of free calls in halt callback. This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * mxc_fec: fix some erroneous PHY accesses.javier Martin2009-11-11-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes erroneous access to the ethernet PHY which broke the driver. 1. Selector field in the auto-negotiation register must be 0x00001 for using 802.3, not 0x00000 which is reseved. 2. Access to the PHY address specified by CONFIG_FEC_MXC_PHYADDR, not 0x0 fixed address. This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains. Now using proper defines for auto-negotiation register. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Fix SMC91111 regression: lpd7a40x build failuresBen Warren2009-11-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | Both lpd7a400 and lpd7a404 failed to compile because they had CONFIG_SMC_USE_IOFUNCS defined: examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw' Also removed an orphaned paren in lpd7a404.h Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * SMC91111: Clean up SMC_inx macros on xsengine and xaeniaxBen Warren2009-11-09-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warnings: Configuring for xaeniax board... smc91111_eeprom.c: In function 'print_macaddr': smc91111_eeprom.c:278: warning: suggest parentheses around + or - in operand of & smc91111_eeprom.c:281: warning: suggest parentheses around + or - in operand of & ... Configuring for xsengine board... smc91111_eeprom.c: In function 'print_macaddr': smc91111_eeprom.c:278: warning: suggest parentheses around + or - inside shift smc91111_eeprom.c:281: warning: suggest parentheses around + or - inside shift Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Fix CS8900 regression on impa7 boardBen Warren2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | The following error was seen on impa7 board, due to its use of a 32-bit bus on CS8900. cs8900.c:137:37: error: macro "get_reg_init_bus" passed 2 arguments, but takes just 1 This patch gives the macro the correct number of arguments Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * clarify eth driver halt/recv stepsMike Frysinger2009-11-09-5/+8
| | | | | | | | | | | | | | | | The dev->halt() func can be called at any time, and the dev->recv() func does not need to use NetRxPackets[] when calling NetReceive(). Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Fix cs8900 dev->priv not init issueHui.Tang2009-11-09-3/+4
| | | | | | | | | | | | | | Ensure all CS8900 data structures are assigned before accessing device Signed-off-by: Hui.Tang <zetalabs@gmail.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Fix DM9000 MAC address handlingBen Warren2009-10-29-12/+14
| | | | | | | | | | | | | | | | Proper behavior is to pull MAC address from NVRAM in the initialization() an stuff it in dev->address, then program the device from dev->address in the init() function. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-11-11-2/+2
|\ \
| * | ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | | This error only appears when DEBUG is enabled in this driver. That's why it went unnoticed till now. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem only seen very occasionally on Canyonlands. The NOR flash interface (CFI driver) doesn't work reliably in all cases. Erasing and/or programming sometimes doesn't work. Sometimes with an error message, like "flash not erased" when trying to program an area that should have just been erased. And sometimes without any error messages. As mentioned above, this problem was only seen rarely and with some PLL configuration (CPU speed, EBC speed). Now I spotted this problem a few times, when running my Canyonlands with the following setup (chip_config): 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 Changing the EBC configuration to not release the bus into high impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1 in EBC0_CFG) seems to fix this problem. I haven't seen any failure anymore with this patch applied. Signed-off-by: Stefan Roese <sr@denx.de> Cc: David Mitchell <dmitchell@amcc.com> Cc: Jeff Mann <MannJ@embeddedplanet.com>
* | | Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-11-09-1/+142
|\ \ \
| * | | ARM: Use Linux version for unaligned access codeRemy Bohmer2009-11-07-1/+142
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The asm-arm/unaligned.h includes linux/unaligned/access_ok.h This file is unsafe to be used on ARM, since it does an unaligned memory accesses which fails on ARM. Lookin at Linux the basic difference seems to be the header "include/asm-arm/unaligned.h". The Linux version of "unaligned.h" does *not* include "access_ok.h" at all. It includes "le_byteshift.h" and "be_byteshift.h" instead. Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Stefan Roese <sr@denx.de> -- include/asm-arm/unaligned.h | 3 - include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++ include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 include/linux/unaligned/be_byteshift.h create mode 100644 include/linux/unaligned/le_byteshift.h
* | | ppc/85xx: Fix inclusion of 83xx immap in 85xx buildsKumar Gala2009-11-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should not be including the immap_83xx.h when building 85xx. We can just get this all from common.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | 86xx: Remove redundant code in initdramBecky Bruce2009-11-04-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | The same code exists both inside an #ifdef and outside of it. Remove the extra code for all the 86xx boards. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl_pci_init_port end-point initialization is brokenEd Swarthout2009-11-04-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-28/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/85xx: Fix misc L2 cache enabling bugDave Liu2009-10-31-4/+8
|/ / | | | | | | | | | | | | We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-10-31-69/+54
|\ \
| * | sh: Update lowlevel_init.S of espt-gigaNobuhiro Iwamatsu2009-10-30-9/+1
| | | | | | | | | | | | | | | | | | | | | There was the point that did not use write macro. Change to write macro. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Move some defs to convince 'pcrel too far'Nobuhiro Iwamatsu2009-10-30-54/+53
| | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Takashi Yoshii <yoshii.takashi@gmail.com>
| * | sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios.Nobuhiro Iwamatsu2009-10-30-6/+0
| |/ | | | | | | | | | | | | | | By "arm/microblaze/nios/nios2/sh: Remove relocation fixups" (commit: 0630535e2d062dd73c1ceca5c6125c86d1127a49", doesn't need malloc_bin_reloc function. This commit remove this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sbc8349: fix incorrect commentWolfgang Denk2009-10-28-1/+1
|/ | | | | | | | The comment for the BR0_PRELIM port size initialization incorrectly stated 32 bit, while it's actually 16 bit. The code is correct. Reported-by: Guenter Koellner <guenter.koellner@nsn.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-10-28-133/+175
|\
| * cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-133/+175
| | | | | | | | | | | | | | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sparcWolfgang Denk2009-10-28-2/+2
|\ \
| * | Fix bug in jumptable call stubs for SPARC.Sergey Mironov2009-10-27-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Sergey Mironov <ierton@gmail.com> Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* | | Fix Compliation warning for TNY-A9260 and TNY-A9G20Sandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Fix Compliation warning for SBC35-A9G20 boardSandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | galaxy5200: Add default environment variablesEric Millbrandt2009-10-28-2/+8
| |/ |/| | | | | | | | | | | Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* | Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-56/+6210
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Add 'editenv' commandPeter Tyser2009-10-27-0/+43
| | | | | | | | | | | | | | | | | | The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | setenv(): Delete 0-length environment variablesPeter Tyser2009-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Previously setenv() would only delete an environment variable if it was passed a NULL string pointer as a value. It should also delete an environment variable when it encounters a valid string pointer of 0-length. This change/fix is generally useful and is necessary for the upcoming "editenv" command. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | readline(): Add ability to modify a string bufferPeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | If the 'buf' parameter is a non-0-length string, its contents will be edited. Previously, the initial contents of 'buf' were ignored and the user entered its contents from scratch. This change is necessary to support the upcoming "editenv" command but could also be used for future commands which require a user to modify an existing string. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | cread_line(): Remove unused variablesPeter Tyser2009-10-27-4/+1
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Check for NULL prompt in readline_into_buffer()Peter Tyser2009-10-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, passing readline() or readline_into_buffer() a NULL 'prompt' parameter would result in puts() printing garbage when CONFIG_CMDLINE_EDITING was enabled. Note that no board currently triggers this bug. Enabling CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in the bug appearing. This change is only intended to prevent someone from running into this issue in the future. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | drivers/net/phy/miiphybb.c: fix warning: no newline at end of fileWolfgang Denk2009-10-27-1/+1
| | | | | | | | | | | | | | | | Add missing newline. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com> Cc: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-10-27-81/+460
|\ \
| * | mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | xpedite5370: Enable multi-core supportPeter Tyser2009-10-27-4/+17
| | | | | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-28 23:34:14 +0000