| Commit message (Collapse) | Author | Age | Lines |
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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..in board pci.c files
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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need to rm it from pci code, too!
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Make libfdt the default for the WRS SBC8349 board.
Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef
done for the other 83xx based boards. Also fix a typo in CONFIG_PCI.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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This adds libfdt support code for the Wind River sbc8349 board.
Parallel of commit 3fde9e8b22cfbd7af489214758f9839a206576cb for
the other Freescale 83xx boards.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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ECC code is now shared for all 83xx boards, so remove board specific one.
See commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 for reference.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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The MPC8360E MDS config defined:
CONFIG_OF_HAS_BD_T
CONFIG_OF_HAS_UBOOT_ENV
Which we don't use or ever needed. This seems like copy-paste feature creep.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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mpc8360emds.c: In function ‘ft_board_setup’:
mpc8360emds.c:335: warning: assignment discards qualifiers from pointer target type
mpc8360emds.c:345: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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rename to fdt_path_offset
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x.
This change guarantees that the environment will be located on the
first flash sector after the U-Boot image.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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u-boot itself uses GMII mode on the 8360. Fix up UCC phy-connection-type
properties in the device tree so the PHY gets configured for internal delay on
RX only by the OS, as prescribed by mpc8360 rev. 2.1 pb mds erratum #2.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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update the CREDITS and MAINTAINERS.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Add the MAINTAINER and MAKEALL entries for mpc837xemds
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Add the README.mpc837xemds to /doc
Signed-off-by: Dave Liu <daveliu@freescale.com>
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The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
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The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Despite user manual, BCSR9.7 is negated (high) on HRST, so
UART2 is disabled. Fix that and configure QE pins properly.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
currently-defined 83xx boards. This change guarantees that the environment
will be located on the first flash sector after the U-Boot image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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ext2fs_read_file() had the function arguments swapped.
Pointed out by Mike Montour, 19 Dec 2007 22:34:25 -0800
Signed-off-by: Wolfgang Denk <wd@denx.de>
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The MPC5200 OHCI controller operates in big endian, so
CFG_OHCI_BE_CONTROLLER must be defined for it to work properly.
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch updates the fw_printenv/fw_setenv userspace tool to include
the correct MTD header in order to compile against current kernel
headers. Backward compatibility is preserved by introducing an option
MTD_VERSION which can be set to "old" for compilation using the old MTD
headers. Along with this a number of warnings are fixed.
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
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On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
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The privious 4xx POST implementation only supported storing the POST
WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
we need to store the POST WORD in some other non volatile location.
This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
a location.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well
Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.
Signed-off-by: Stefan Roese <sr@denx.de>
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Some operating systems rely on assigned PCI interrupts.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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This patch updates the PLB/PCI divider when running at
400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Add CFG_NAND_QUIET_TEST option to disable error message when
no NAND chip is installed on PMC440 boards.
Disable a couple of config defines that are only used for NAND_U_BOOT.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Disabled and remove inka4x0 custom flash driver, use CFI flash
driver instead.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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- Cleanup compile warnings.
- Add missing '\0' in default environment.
- Increase CFG_MONITOR_LEN to 256 KiB.
- Add required CFG_USE_PPCENV.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Now that there are no board-specific versions of
"denali_core_search_data_eye()", the weak binding on the common version
can be removed.
Signed-off-by: Larry Johnson <lrj@acm.org>
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Signed-off-by: Stefan Roese <sr@denx.de>
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On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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