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* MXSCM-267 mx6dqscm: set hdmi as primary display for qwks boardscm-imx_v2016.03_4.1.15_2.0.0_gaJuan Gutierrez2017-03-09-2/+10
| | | | | | | For the out of the box experience, the primary display for the QWKS board is set tot HDMI. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-266 mx6dqscm: increase lpddr2 voltage to 1.25VJuan Gutierrez2017-03-09-2/+2
| | | | | | | From testing the performance is better when the voltage for lpddr2 is set to 1.25V instead of 1.2V. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-245 mx6scm: additional scm board support for 6dq and 6sxJuan Gutierrez2017-01-31-1/+65
| | | | | | | | | | | | Add aditional support for MX6DQSCM and MX6SXSCM boards like: - MX6DQSCM 2GB EVB - MX6DQSCM 512MB EVB - MX6DQSCM 512MB QWKS - MX6SXSCM EPOP EVB - MX6SXSCM 512MB EVB Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-244 mx6dqscm: adjust drive strength for scm i.mx6dq partsJuan Gutierrez2017-01-31-118/+114
| | | | | | | | | From experimentation a DSE value of 60ohms shows better results for both 2GB and 1GB MXDQSCM parts. The failure rate part using the memtest improves using this value for DSE. This adjusment is performed in the corresponfing imximage_scm_lpddr2.cfg file. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-237 mx6dqscm: qwks: add support for qwks rev3Juan Gutierrez2017-01-31-1/+32
| | | | | | | | | | | Support for the i.MX SX SCM QWKS rev3. The new revision has support for ov5642 camera, bluetooth and wifi support. Providing configuration files for: - Regular 1gb board - spinor Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-236 mx6dqscm: adjust some ddr calibration parametersJuan Gutierrez2017-01-31-13/+16
| | | | | | | | | | | Some adjustment to the ddr configuration like: - Precharge all commands per JEDEC - Fix the space partition values for 2Gb - Fix other values that reduce yield of scm parts per testing perfomed Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-222 usb: fix swbst_mode to properly power usbJuan Gutierrez2017-01-31-1/+1
| | | | | | | | | | The definition of the SWBST_MODE_AUTO at the pfuze100_pmic.h file changed between uboot versions. On the previous version the shift to the proper bit field was part of the macro. In the uboot v2016 this macro does not include the shift and needs to be performed explicitly to properly modify the SWBST_MODE bit field. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-213: remove dmfc from boot arguments for mx6scm boardsJuan Gutierrez2017-01-31-5/+2
| | | | | | | | | | | | Intially this parameter was added to fix a video stuttering but with L4.1 the video issue is not present so we can safely get rid of this parameter. When using both ldb interfaces in separate mode and passing the dmfc argument as boot parameter to the kernel, a distortion on both displays is observed when rendering to the secondary display. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-212: mx6dqscm: usb: fix usb_otg_id iomux pad settingsJuan Gutierrez2017-01-31-0/+8
| | | | | | | | | | USB_OTG_ID iomux pad was missconfigured and not selecting the GPIO1 Alternative for QWKS and the ENET_RX_ERR for EVB, as a consequence when connecting a USB device the PWR_EN was disabled. So usb function like "usb start" was not working as it should. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13292 mx6sxscm: evb: add support for epop evb boardAlejandro Sierra2017-01-31-0/+5
| | | | | | | | | Support for the ePOP i.MX SX SCM Evaluation Board (EVB) This provides the configuration files for 512mb and emmc support. Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13290 mx6sxscm: evb: add support for 1gb evb boardAlejandro Sierra2017-01-31-0/+15
| | | | | | | | | | | | Support for the i.MX SX SCM Evaluation Board (EVB) Providing configuration files for - Regular 1gb board - m4fastup configuration - qspi2 support Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13289 imx: mx6sxscm: generic mx6sxscm board supportJuan Gutierrez2017-01-31-0/+1435
| | | | | | | | | | | | | | Provide the generic support for i.MX6SX SCM boards i.MX6SX SCM board file with the generic configuration, LPDDR2 memory calibration and build support is provided. - LPDDR2 memory configuration files for 1GB and 512MB. - plugin support for the above configurations. - driver support for: uart, qspi, i2c, usb, mmc. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13258 mx6dqscm: evb: support for 1Gb SCM EVB boardJuan Gutierrez2017-01-31-0/+10
| | | | | | | | | Support for the 1GB SCM Evaluation board (EVB) 2 defconfig files are provided for EVB: Android and SD Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13256 mx6dqscm: qwks: add support for 1Gb SCM QWKS boardJuan Gutierrez2017-01-31-0/+15
| | | | | | | | | | | | Support for the 1GB SCM Quick Start board (QWKS) - 3 defconfig files are provided for QWKS: Android, Regular SD and SPI-NOR - SD and or SPI-NOR boot are supported on fix mode. - Due to performance, interleave is the default mode for Android. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13255 imx: mx6dqscm: generic mx6dqscm board supportJuan Gutierrez2016-10-24-0/+3161
| | | | | | | | | | | | | Provide the generic support for i.MX6DQ SCM boards - LPDDR2 memory configuration files for 1GB, 2GB and 512MB. - plugin support for the above configurations. - fix and interleave memory mode (selected by CONFIG option) - driver support for: uart, spi, i2c, usb, sata and fec. - Android support Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13131: mx6qarm2: add fastboot and recovery supportrel_imx_4.1.15_2.0.0_gaAdrian Alonso2016-09-15-0/+33
| | | | | | | Add fastboot and recovery mode support for mx6qarm Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry picked from commit 505e899ce582118da28ca1f4487ce7f179225bd7)
* MLK-13130: configs: mx6qarm2: android lpddr2 pop supportAdrian Alonso2016-09-15-1/+94
| | | | | | | Add Android support for mx6qarm2 lpddr2 pop target Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c)
* MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividersAdrian Alonso2016-09-15-1/+1
| | | | | | | | | Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
* MLK-13141 mx6qpsabresd: Do not touch VGEN3 and VGEN5Robin Gong2016-08-30-12/+14
| | | | | | | | | VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board, so software didn't need to change their voltage output anymore. Otherwise, VGEN3 will be wrongly updated from 1.8v to 2.8v. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73)
* MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse settingBai Ping2016-08-30-5/+0
| | | | | | | | | | | | | | | | | On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)
* MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping2016-08-25-6/+32
| | | | | | | | | | | | | | | | | Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13115 imx: mx6ullevk: Update LPDDR2 script for i.MX6ULL 9x9 EVKYe Li2016-08-23-4/+4
| | | | | | | | | | | | | | | | | | Update the LPDDR2 script to 1.2 rev with delay line settings changed. File: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx Changes: Update Delay Line Settings based on the delay line calibration results of more boards. MMDC_MPRDDLCTL = 0x40403439 MMDC_MPWRDLCTL = 0X4040342D Test: One 9x9 EVK board pass stress memtester. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13070 imx: mx6ullevk: Add 9x9 EVK supportYe Li2016-08-12-21/+27
| | | | | | | | | | | | | | | | Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script for the board to version 1.0. DDR script: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc Changes: Initial version Test: Passed memtester overnight test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2016-07-29-1/+322
| | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATAYe Li2016-07-29-4/+14
| | | | | | | | | | | | | | We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before this changing, SATA read/write can't work after it. And we have to re-init SATA. The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing. This patch is an work around that moves the ENET clock setting (enable_fec_anatop_clock) from ethernet init to board_init which is prior than SATA initialization. So there is no PLL6 change after SATA init. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12998 imx: mx6ullevk: Add build targets for boot devicesYe Li2016-07-26-0/+15
| | | | | | Add build targets for eMMC, NAND and QSPI NOR. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12964 imx: enlarge mux width to 4Peng Fan2016-07-22-8/+7
| | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVKYe Li2016-07-19-0/+2088
| | | | | | | | | | | | | | | | | | | | | Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok to work. The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when it is needed. The DDR3 script is using version 1.2: File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc Test: 3 boards passed memtester. Build target: mx6ull_14x14_evk_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12985 imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-07-15-0/+5
| | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Ye.Li <ye.li@nxp.com>
* dfu: avoid memory leakPeng Fan2016-07-01-1/+3
| | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> (cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
* MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ullBai Ping2016-06-08-0/+7
| | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-12889 mx6ullarm2: Update DDR script to version 2.2Ye Li2016-06-08-2/+2
| | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.inc Changes: Change MMDC_MDMISC.WALAT to 1 setmem /32 0x021B0018 = 0x00211740 Test: Passed memtester on two mx6ull ddr3 arm2 boards Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12888 usb: ehci: only shutdown opened controllerPeng Fan2016-06-06-0/+4
| | | | | | | | | | | | | | | | If the usb controller is not running, no need to shutdown it, otherwise `usb stop` complains about: "EHCI failed to shut down host controller". To i.MX7D SDB, there are two usb ports, one Host, one OTG. If we only plug one udisk to the Host port and then `usb start`, the OTG controller for OTG port does not run actually. Then, if `usb stop`, the OTG controller for OTG port will also be shutdown, but it is not running. This patch adds a check that only shutdown the running controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12883 usb: limit USB_MAX_XFER_BLK to 256Peng Fan2016-06-06-1/+3
| | | | | | | | | | | | | | | | | | | For Some USB mass storage devices, such as: " - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x0930 Product 0x6545 Version 1.16 " When `usb read 0x80000000 0 0x2000`, we met "EHCI timed out on TD - token=0x80008d80". The devices does not support scsi VPD page, we are not able to get the maximum transfer length for READ(10)/WRITE(10). So we limit this to 256 blocks as READ(6). Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
* MLK-12852 ocotp: mxc: mx6ull: fix GP3/GP4 progPeng Fan2016-06-03-1/+7
| | | | | | | | | | | | Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word' is not correct when program bank 8, since ocotp controller actully use word index. For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67. But actully it should be (7 << 3 | 7) ---> 63. So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12865 Nand: Fix BCH debug1 register access issueYe Li2016-05-31-1/+1
| | | | | | Should have "&" to access the register address, otherwise uboot will hang. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12848: mx6ull_14x14_ddr3_arm2: add new TSC configHaibo Chen2016-05-24-0/+21
| | | | | | | | Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2 board, disable PMIC and ldo bypass check. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-12845 imx: mx6sabre_common: fix mmcargsPeng Fan2016-05-23-2/+2
| | | | | | | A space should be added after ${smp}. If not, bootargs is wrong, when CONFIG_SYS_NOSMP defined. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-23-0/+9
| | | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
* MLK-12798 imx6ull: fix snvs tamper pin usagePeng Fan2016-05-16-16/+30
| | | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable using these pins. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12775 mx6ullarm2: Add package size info to the build target and dtb fileYe Li2016-05-11-1/+1
| | | | | | | | To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL naming rule to process i.MX6ULL. Signed-off-by: Ye Li <ye.li@nxp.com>
* imx: iomux-v3: fix UART input selectsStefan Agner2016-05-10-4/+4
| | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2. From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2016-05-09-24/+34
| | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12766 net: fec: do not access reserved register for i.MX6ULLPeng Fan2016-05-09-1/+1
| | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6ULL. Accessing these register will cause enet not work well or cause system report fault. Reported-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-14/+14
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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