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* Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-11-2924/+50912
|\ | | | | | | | | | | | | Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-09-13/+982
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| | * sun7i: Add bananapi boardHans de Goede2014-07-31-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Banana Pi is an A20 based development board using Raspberry Pi compatible IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi and stereo audio out + various expansion headers: http://www.lemaker.org/ Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: HYP/non-sec: configure CNTFRQ on all CPUsMarc Zyngier2014-07-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CNTFRQ needs to be properly configured on all CPUs. Otherwise, virtual machines hoping to find valuable information on secondary CPUs will be disapointed... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: HYP/non-sec: add sun7i PSCI backendMarc Zyngier2014-07-31-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: Add support for a number of new sun7i boardsHans de Goede2014-07-31-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun5i: Add support for a number of new sun5i boardsHans de Goede2014-07-31-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun4i: Add support for a number of new sun4i boardsHans de Goede2014-07-31-2/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: Add CONFIG_MACPWR optionHans de Goede2014-07-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | On some boards the ethernet-phy needs to be powered up through a gpio, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: Enable EHCI on various sunxi boardsHans de Goede2014-07-31-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Most sunxi boards have the EHCI controller hooked up, enable it on all relevant boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun5i: add USB EHCI settingsHans de Goede2014-07-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun5i if CONFIG_USB_EHCI is enabled. Note we don't specify default VBUS gpio pins for sun5i since they vary too much from board to board. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun4i: add USB EHCI settingsHans de Goede2014-07-31-0/+12
| | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun4i if CONFIG_USB_EHCI is enabled. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * cubieboard2: Enable AXP209 power controllerIan Campbell2014-07-31-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: cubietruck: enable USB EHCIRoman Byshko2014-07-31-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cubietruck has two USB host controllers. This makes them usable by enabling the EHCI driver for them. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Also enable ehci for Cubietruck_FEL] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: add USB EHCI settingsRoman Byshko2014-07-31-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun7i if CONFIG_USB_EHCI is enabled. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Use SUNXI_GPH macro for SUNXI_USB_VBUS#_GPIO] [hdegoede@redhat.com: Add #ifndef SUNXI_USB_VBUS#_GPIO to allow override of the default pins from boards.cfg] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add general USB settingsRoman Byshko2014-07-31-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General configuration settings to be set if CONFIG_USB_EHCI is enabled for an Allwinner aka sunxi SoC. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add USB EHCI driverRoman Byshko2014-07-31-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add defines to control USB Host clocks/resetsRoman Byshko2014-07-31-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit adds three defines which will be used in the EHCI driver to enable USB clock and assert reset controllers of the corresponding PHYs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-31-9/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | Prepare v2014.10-rc1Tom Rini2014-08-06-2/+2
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | Change Andy Fleming's email addressAndy Fleming2014-08-06-5/+5
| | | | | | | | | | | | | | | | | | | | | Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com>
| * | The _config target is not present anymore, mention _defconfig insteadHolger Freyther2014-08-06-11/+11
| | | | | | | | | | | | | | | The _config part is gone for sure, the _defconfig target could at least work. I have not verified this for all targets though.
| * | git-mailrc: add a kconfig aliasStephen Warren2014-08-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc alias. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | doc: README.SPL: adjust for Kbuild and KconfigMasahiro Yamada2014-08-06-22/+6
| | | | | | | | | | | | | | | | | | Reflect the latest build system to doc/README.SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | doc: delete README.ARM-SoCMasahiro Yamada2014-08-06-31/+0
| | | | | | | | | | | | | | | | | | This document is too old and useless. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-08-06-8/+31
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| | * | spi, spi_mxc: do not hang in spi_xchg_singleHeiko Schocher2014-08-06-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | spi: Support half-duplex mode in FDT decodeSimon Glass2014-08-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This parameter should also be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | exynos: spi: Fix calculation of SPI transaction start timeSimon Glass2014-08-06-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | cros_ec: Fix two bugs in the SPI implementationSimon Glass2014-08-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An incorrect message version is passed to the EC in some cases and the parameters of one function are switched. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | sf: sf_ops: Stop leaking memoryMarek Vasut2014-08-06-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | It's usually a common pattern to free() the memory that we allocated. Implement this here to stop leaking memory. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+83
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| | * | kmp204x: prepare to use CPU watchdogBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch configures the qrio to trigger a core reset on a CPU reset request. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x/qrio: support for setting the CPU reset request modeBoschung, Rainer2014-08-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN flag in the qrio RESCNF reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x: set CPU watchdog reset reason flagBoschung, Rainer2014-08-01-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x/qrio: prepare support for the CPU watchdog reset reasonBoschung, Rainer2014-08-01-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog flag in the REASON1 reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x: CPU watchdog enabledBoschung, Rainer2014-08-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc: macros for e500mc timer regs addedBoschung, Rainer2014-08-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | Merge http://git.denx.de/u-boot-dmTom Rini2014-08-04-0/+17
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| | * | | arm: Support pre-relocation malloc()Simon Glass2014-08-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for re-relocation malloc() in arm's start-up code. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | arm: Set up global data before board_init_f()Simon Glass2014-08-04-0/+11
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that the global_data pointer is set up in board_init_f(). However it is actually set up before this, it just isn't zeroed. If we zero the global data before calling board_init_f() then we don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA. Make this change (on arm32 only) to simplify the init process. I don't have the ability to test aarch64 yet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com>
| * | | env_mmc: support env partition setup in runtimeDmitry Lifshitz2014-08-01-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add callback with __weak annotation to allow setup of environment partition number in runtime from a board file. Propagate mmc_switch_part() return value into init_mmc_for_env() instead of -1 in case of failure. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | env_mmc: add mmc_get_env_addr() prototypeDmitry Lifshitz2014-08-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing mmc_get_env_addr() prototype in environment.h Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | MMC: atmel_mci: enable high speed mode supportBo Shen2014-08-01-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the MCI IP version >= 0x300, it supports hight speed mode option, this patch enable it. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | MMC: atmel_mci: add configuration register definitionBo Shen2014-08-01-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configuration register definition, this register only exists on MCI IP version >= 0x300. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | MMC: atmel_mci: refactor setting the mode registerBo Shen2014-08-01-14/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mode register is different between MCI IP version. So, according to MCI IP version to set the mode register. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc/dw_mmc: Fix clock divider calculation error for bypass modeChin Liang See2014-08-01-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
generated by cgit v1.1 at 2024-11-28 17:31:29 +0000