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* x86: kconfig: Hide "System tables" for EFIBin Meng2015-08-26-3/+1
| | | | | | | Instead of hiding each menu entries under "System tables" for EFI, hide the main menu completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Allow >=4GiB memory bank sizeBin Meng2015-08-26-5/+4
| | | | | | | Some platforms may have >=4GiB memory, so we need make U-Boot report such configuration correctly when booting as the coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove calculate_relocation_address()Bin Meng2015-08-26-60/+2
| | | | | | | Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Correctly report E820 typesBin Meng2015-08-26-2/+13
| | | | | | | coreboot has some extensions (type 6 & 16) to the E820 types. When we detect this, mark it as E820_RESERVED. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Increase memrange entry number to 32Bin Meng2015-08-26-6/+3
| | | | | | | | | Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Update coreboot payload entry point addressBin Meng2015-08-26-3/+3
| | | | | | | | With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* net: e1000: Fix build warnings for 32-bitBin Meng2015-08-26-4/+5
| | | | | | | | | | | | | | | | commit 6497e37 "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge git://git.denx.de/u-boot-pxaTom Rini2015-08-24-88/+94
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| * arm: pxa: colibri_pxa270: add optional i2c supportMarcel Ziswiler2015-08-24-0/+9
| | | | | | | | | | | | This is useful once Andrew's PXA I2C driver gets merged. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: colibri_pxa270: add optional lcd supportMarcel Ziswiler2015-08-24-0/+13
| | | | | | | | | | | | | | | | Add optional LCD support. Note that depending on the toolchain used one might have to drop some other features to stay within the 0x40000 size limit. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: colibri_pxa270: add some more nor flash detailsMarcel Ziswiler2015-08-24-0/+4
| | | | | | | | | | | | | | Add some more NOR flash details like size, bus width and lock/unlock time outs. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: palmtreo680: get rid of obsolete CONFIG_SYS_LCD_PXA_NO_L_BIASMarcel Ziswiler2015-08-24-1/+0
| | | | | | | | | | | | | | Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere else throughout the U-Boot sources any more. Drop it. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * lcd: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-5/+4
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * usb: pxa27x_udc: clean-up include file orderMarcel Ziswiler2015-08-24-3/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * serial: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-2/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: mmc: clean-up include file orderMarcel Ziswiler2015-08-24-5/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-3/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: use common timer functionsAndrew Ruder2015-08-24-69/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
| * pxa: Fix boot hang by avoiding vector relocationAndrew Ruder2015-08-24-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") pxa does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the pxa SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows pxa to boot again. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-08-24-4/+4
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| * MIPS: fix syntax for fdt_chosen/initrd.Govindraj Raja2015-08-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | The syntax for the fdt_chosen/initrd functions seem to deprecated in usage from MIPS bootm implementation. Third parameter is no more used in these api's Refer to : include/fdt_support.h Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
| * mips: Use unsigned int when reading c0 registersChris Packham2015-08-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms started using common the common timer functions which are based around the fact that many platforms have a 32-bit free running counter register that can be used see commit 8dfafdd (Introduce common timer functions). Even MIPS64 has such a 32-bit register (some have an additional 64-bit free running counter, but that's something for another time). The problem is that in __read_32bit_c0_register() we read the value from this register into an _signed_ int and as it's returned up the call chain to timer_read_counter() it gets assigned to an unsigned long. On a 32-bit system there is no problem. On a 64-bit system odd things happen, sign extension seems to kick in and all of a sudden if the counter register happens to have the MSb (i.e. the sign bit) set the negative int gets sign extended into a very large unsigned long value. This in turn throws out things from get_ticks() up. Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There seems to be little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-23-2760/+3220
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: socfpga: Fix ArriaV SoCDK PLL configMarek Vasut2015-08-23-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Enable ethernet on ArriaV SoCDKMarek Vasut2015-08-23-0/+3
| | | | | | | | | | | | | | | | | | | | | Synchronise the config options with Cyclone V SoCDK and other boards. This enables ethernet on the ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix SD/MMC boot on ArriaV SoCDKMarek Vasut2015-08-23-0/+6
| | | | | | | | | | | | | | | | | | | | | Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDKMarek Vasut2015-08-23-9/+4
| | | | | | | | | | | | | | | | | | Repair the maintainer entries so they match the current state of code. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Enable DWAPB GPIO driverMarek Vasut2015-08-23-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: dts: Add bank-name property to each GPIO bankMarek Vasut2015-08-23-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add "bank-name" property to each GPIO bank to give it unique name. The approach here is exactly the same as with the "regulator-name" property for regulators. Signed-off-by: Marek Vasut <marex@denx.de>
| * | gpio: Add DW APB GPIO driverMarek Vasut2015-08-23-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | Add driver for the DesignWare APB GPIO IP block. This driver is DM capable and probes from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-23-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-23-2982/+2546
| | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Add qts-filter.sh scriptMarek Vasut2015-08-23-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Remove AV-specific parts from CV-SoCDKMarek Vasut2015-08-23-1153/+0
| | | | | | | | | | | | | | | | | | | | | Just remove the ArriaV specific parts from the CycloneV SoCDK board and they are no longer needed now. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Remove CV-specific parts from AV-SoCDKMarek Vasut2015-08-23-1117/+0
| | | | | | | | | | | | | | | | | | | | | Just remove the CycloneV specific parts from the ArriaV SoCDK board and they are no longer needed now. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-23-2/+2773
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Unbind CPU type from board typeMarek Vasut2015-08-23-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-23-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Do not enable gmac1 in Cyclone V dtsiMarek Vasut2015-08-23-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GMAC which is enabled is purely board property, so do not enable arbitrary GMAC in DT include files. Same goes for PHY mode, which is again a board property. The CycloneV SoCDK does this correctly, but SoCrates doesn't. This bug never manifested itself though, since all the boards ever used the GMAC1 . This bug manifests itself only on boards that utilise GMAC0. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Make the DT mmc node consistentMarek Vasut2015-08-23-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node. This makes aliases not very usable, so make everything into mmc0. Moreover, zap the useless mmc alias while at this. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix delay in clock managerMarek Vasut2015-08-23-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix delay in freeze controllerMarek Vasut2015-08-23-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ddr: altera: Repair uninited variableMarek Vasut2015-08-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following problem: drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full': drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized] if (found_passing_read && found_failing_read) ^ drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here u32 found_passing_read, found_failing_read, initial_failing_dtap; ^ Signed-off-by: Marek Vasut <marex@denx.de>
| * | ddr: altera: Replace float multiplication with integer oneMarek Vasut2015-08-23-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gem is really really rare, there was an actual float used in the Altera DDR init code, which pulled in floating point ops from the libgcc, just wow. Since we don't support floating point operations the same way Linux does not support them, replace this with an integer multiplication and division combo. This removes some 2kiB of size from the SPL as the floating point ops are no longer pulled in from libgcc. This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which does not contain the floating point bits. Signed-off-by: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-08-23-447/+1103
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| * | net: Move CONFIG_E1000 options to KconfigSimon Glass2015-08-21-36/+508
| | | | | | | | | | | | | | | | | | | | | | | | Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | Tidy up some defconfig filesSimon Glass2015-08-21-192/+165
| | | | | | | | | | | | | | | | | | | | | | | | Several files are out of order. This means that when the moveconfig tool moves CONFIG options to Kconfig it generates a large diff. To avoid this, reorder the files first. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | net: e1000: Add Kconfig optionsSimon Glass2015-08-21-10/+32
| | | | | | | | | | | | | | | | | | | | | Add Kconfig options in preparation for moving boards to use Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: e1000: Convert to driver modelSimon Glass2015-08-21-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to support driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
| * | net: e1000: Prepare for driver model conversionSimon Glass2015-08-21-200/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid using it in the driver unless necessary. Most of the time it is better to pass the private driver pointer anyway. Also refactor the code so that code that the driver model implementation will share are available in functions that can be called. Add stubs where necessary. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
generated by cgit v1.1 at 2024-12-26 11:15:19 +0000