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* tegra114: fdt: add compatible string for tegra114 SPI ctrlAllen Martin2013-03-25-0/+2
| | | | | | | | Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* sf: winbond: add W25Q32DWAllen Martin2013-03-25-0/+5
| | | | | | | | Add support for Winbond W25Q32DW 32Mbit part Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-46/+224
| | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra20: spi: move fdt probe to spi_initAllen Martin2013-03-25-43/+67
| | | | | | | | | | Make the tegra20 SPI driver similar to the tegra30 (and soon to be tegra114) SPI drivers in preparation of common fdt SPI driver front end. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: pull register structs out of headersAllen Martin2013-03-25-110/+110
| | | | | | | | | | Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: remove non fdt supportAllen Martin2013-03-25-37/+4
| | | | | | | | | Remove non fdt support from tegra20 and tegra30 SPI drivers in preparation of new common fdt based SPI driver front end. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-13/+13
| | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: remove support for UART SPI switchAllen Martin2013-03-25-202/+3
| | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-24-397/+2037
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| * mmc: omap_hsmmc.c: only register getcd/getwp callbacks if gpio could be usedPeter Korsgaard2013-03-24-2/+6
| | | | | | | | | | | | | | | | | | Gets rid of warnings from omap_gpio: ERROR : check_gpio: invalid GPIO -1 (and undefined behaviour as the -1 error code is interpreted as gpio value) Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * mmc: mmc_getcd/getwp: use sensible defaultsPeter Korsgaard2013-03-24-4/+12
| | | | | | | | | | | | | | | | | | Let mmc_getcd() return true and mmc_getwp() false if mmc driver doesn't provide handlers for them. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Add braces around first if test in each case to fix warning] Signed-off-by: Tom Rini <trini@ti.com>
| * arm: Correct CONFIG_STANDALONE_LOAD_ADDR for AM33XX/OMAP* platformsTom Rini2013-03-24-1/+1
| | | | | | | | | | | | | | | | All of these platforms have memory starting at 0x80000000, so this is the correct CONFIG_STANDALONE_LOAD_ADDR for all of them. Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * am335x_evm: Add better timings for the new BeagleBoard DDR3 partTom Rini2013-03-24-1/+55
| | | | | | | | | | Tested-by: Rao Bodapati <rao@circuitco.com> Signed-off-by: Tom Rini <trini@ti.com>
| * ti814x_evm: add ti814x evm board supportMatt Porter2013-03-24-4/+532
| | | | | | | | | | | | | | | | | | | | Add TI814X EVM board directory, config file, and MAINTAINERS entry. Enable build. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt to recent omap_hsmmc requirements, Matt re-tested] Signed-off-by: Tom Rini <trini@ti.com>
| * ns16550: enable quirks for ti814xMatt Porter2013-03-24-2/+3
| | | | | | | | | | | | | | TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx: support ti814x mmc reference clockMatt Porter2013-03-24-0/+5
| | | | | | | | | | | | | | TI814x has a 192MHz hsmmc reference clock. Select that clock rate when building for TI814x. Signed-off-by: Matt Porter <mporter@ti.com>
| * am33xx: add dmm support to emif4 libraryMatt Porter2013-03-24-0/+22
| | | | | | | | | | | | | | Adds a config_dmm() routine to support TI814X DMM configuration. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx: add ti814x specific register definitionsMatt Porter2013-03-24-21/+71
| | | | | | | | | | | | | | | | Support the ti814x specific register definitions within arch-am33xx. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx: refactor am33xx mux support and add ti814x supportMatt Porter2013-03-24-227/+566
| | | | | | | | | | | | | | | | | | | | AM33XX and TI814X have a similar mux though the pinmux register layout and address space differ. Add a separate ti814x mux include to support the TI814X-specific differences. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * am33xx: refactor am33xx clocks and add ti814x supportMatt Porter2013-03-24-33/+502
| | | | | | | | | | | | | | Split clock.c for am335x and ti814x and add ti814x specific clock support. Signed-off-by: Matt Porter <mporter@ti.com>
| * am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter2013-03-24-76/+144
| | | | | | | | | | | | | | | | | | | | The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx: convert defines from am33xx-specific to generic namesMatt Porter2013-03-24-13/+13
| | | | | | | | | | | | | | | | Eliminate AM33xx specific names to prepare for TI814x support within AM33xx-land. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx: Add required includes to some omap/am33xx codeTom Rini2013-03-24-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | - In arch/arm/cpu/armv7/omap-common/timer.c, drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files that the driver needs but had been relying on <config.h> to bring in. - In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h> - In am335x_evm.h and pcm051.h don't globally include <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h> as that is the only include which defines things the config uses. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
| * igep00x0: Enable CONFIG_CMD_BOOTZEnric Balletbo i Serra2013-03-24-1/+2
| | | | | | | | | | | | | | | | | | | | With v3.9 and later of the Linux Kernel defaulting to multi-platform images with omap2plus_defconfig, uImage isn't builtable anymore by default. Add CONFIG_CMD_BOOTZ so that we can still boot something the kernel spits out. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
| * ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.Enric Balletbo i Serra2013-03-24-1/+1
| | | | | | | | | | | | | | | | Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
| * am335x: Enable DDR PHY dynamic power down bit for DDR3 boardsVaibhav Hiremath2013-03-24-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable DDR PHY dynamic power down bit, which enables powering down the IO receiver when not performing read. This also helps in reducing overall power consumption in low power states (suspend/standby). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * am33xx:ddr:Fix config_sdram to work for all DDRSteve Kipisz2013-03-22-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
| * am335x_evm: Add more variables and switch to DT booting.Koen Kooi2013-03-22-5/+10
| | | | | | | | | | | | | | | | | | | | Make bootcmd run findfdt so that we know what dtb file to load. Add a loadfdt command to load this file in. Make mmcboot pass in ${fdtaddr} and make the mmc section of bootcmd run loadfdt. Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * am335x_evm: Enable CMD_EXT4 and CMD_FS_GENERIC, add bootpart to envKoen Kooi2013-03-22-4/+6
| | | | | | | | | | | | | | | | | | | | | | The kernel is loaded from some form of ext[234] or FAT, depending on the distribution used. We add a bootpart variable to the environment so that we can load from the correct mmc partition as well. We leave CONFIG_CMD_EXT2 for existing scripts that use ext2load. Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * am335x_evm: add support for BeagleBone Black DT nameKoen Kooi2013-03-22-0/+2
| | | | | | | | | | | | | | | | | | | | Cc: Matt Porter <mporter@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Matt Porter <mporter@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Nishanth Menon <nm@ti.com>
| * Initialise correct GPMC WAITx irq for AM33xxMark Jackson2013-03-22-1/+1
| | | | | | | | | | | | | | | | Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Fix it such that WAIT0 irq is enabled instead. Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * Allow AM335x MPU core clock speed to be specified in the board config fileMark Jackson2013-03-22-2/+9
| | | | | | | | | | | | | | | | | | | | Allow AM335x MPU core clock speed to be specified in the board config file. To use, add the following to the board's config file:- #define CONFIG_SYS_MPUCLK <desired clock freq in MHz> Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * cm-t35: add support for loading splash image from NANDNikita Kiryanov2013-03-22-0/+65
| | | | | | | | | | | | | | Add support for loading splash image from NAND Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | ARM: tegra: enable workaround for ARM erratum 716044Stephen Warren2013-03-22-0/+1
| | | | | | | | | | | | Tegra20 requires the workaround for this erratum. Enable it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: implement erratum 716044 workaroundStephen Warren2013-03-22-0/+7
|/ | | | | | | Add common code to enable the workaround for ARM erratum 716044. This will be enabled for Tegra. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: rpi_b: enable SD controller, add related env/cmdsStephen Warren2013-03-20-3/+117
| | | | | | | | | | | Enable the SD controller driver for the Raspberry Pi. Enable a number of useful MMC, partition, and filesystem-related commands. Set up the environment to provide standard locations for loading a kernel, DTB, etc. Provide a boot command that loads and executes boot.scr.uimg from the SD card; this is written considering future extensibilty to USB storage. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* mmc: add bcm2835 driverStephen Warren2013-03-20-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple driver for the BCM2835's SD controller. Workarounds are implemented for: * Register writes can't be too close to each-other in time, or they will be lost. * Register accesses must all be 32-bit, so implement custom accessors. This code was extracted from: git://github.com/gonzoua/u-boot-pi.git master which was created by Oleksandr Tymoshenko. Portions of the code there were obviously based on the Linux kernel at: git://github.com/raspberrypi/linux.git rpi-3.6.y commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley. swarren changed the following for upstream: * Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues. * Remove register logging from read*/write* functions. * Sort out confusion with min/max_freq values passed to add_sdhci(). * Use more descriptive variable names and calculations in IO accessors. * Simplified and commented twoticks_delay calculation. * checkpatch fixes. Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Andy Fleming <afleming@gmail.com>
* video: add a driver for the bcm2835Stephen Warren2013-03-20-0/+144
| | | | | | | | | | | | | | | The firmware running on the bcm2835 SoC's VideoCore CPU manages the display controller. Add a simple "LCD" driver that communicates with the firmware using the property mailbox protocol. This configures the display and frame-buffer to match whatever physical resolution the firmware chosen when booting, which is typically the native resolution of the attached display device, presumably unless otherwise specified in config.txt on the boot media. Enable this driver in the Raspberry Pi board configuration. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* ARM: rpi_b: disable rpi_b dcache explicitlyStephen Warren2013-03-20-0/+1
| | | | | | | | | | There appears to be no implementation of flush_dcache_range() for ARM1176, so explicitly disable dcache support to avoid references to that function from the LCD core in the next patch. This was presumably not noticed before simply because no drivers for the rpi_b were attempting DMA. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* lcd: calculate line_length after lcd_ctrl_init()Stephen Warren2013-03-20-2/+2
| | | | | | | | | | | | | | | | | | When an LCD driver is actually driving a regular external display, e.g. an HDMI monitor, the display resolution might not be known until the display controller has initialized, i.e. during lcd_ctrl_init(). However, lcd.c calculates lcd_line_length before calling this function, thus relying on a hard-coded resolution in struct panel_info. Instead, defer this calculation until after lcd_ctrl_init() has had the chance to dynamically determine the resolution. This needs to happen before lcd_clear(), since the value is used there. grep indicates that no code outside lcd.c uses this lcd_line_length; in particular, no lcd_ctrl_init() implementations read it. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* ARM: rpi_b: use bcm2835 mbox driver to get memory sizeStephen Warren2013-03-20-1/+20
| | | | | | | | | | | The firmware running on the bcm2835 SoC's VideoCore CPU determines how much of the system RAM is available for use by the ARM CPU. Previously, U-Boot assumed that only 128MB was available, since this was the smallest value configured by any public firmware. However, we can now query the actual value at run-time from the firmware using the mbox property protocol. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: bcm2835: add mailbox driverStephen Warren2013-03-20-1/+572
| | | | | | | | | | | | | The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") and the ARM CPU. The ARM CPU is often thought of as the main CPU. However, the VideoCore actually controls the initial SoC boot, and hides much of the hardware behind a protocol. This protocol is transported using the SoC's mailbox hardware module. Here, we add a very simplistic driver for the mailbox module, and define a few structures for the property messages. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-03-18-49/+4203
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| * usb: Add multiple controllers support for EHCI PCIVincent Palatin2013-03-18-9/+16
| | | | | | | | | | | | | | Use the ability to have several active EHCI controller on a system in the PCI EHCI controller implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable USB features for corebootSimon Glass2013-03-18-0/+17
| | | | | | | | | | | | Enable PCI EHCI, storage, keyboard and Ethernet for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * usb: usbeth: smsc95xx: remove EEPROM loaded checkMichael Spang2013-03-18-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | [port of Linux kernel commit bcd218be5aeb by Steve Glendinning] The eeprom read & write commands currently check the E2P_CMD_LOADED_ bit is set before allowing any operations. This prevents any reading or writing unless a correctly programmed EEPROM is installed. Signed-off-by: Michael Spang <spang@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
| * usb: ehci: Fix aliasing issue in EHCI interrupt codeVincent Palatin2013-03-18-1/+1
| | | | | | | | | | | | | | | | | | | | The interrupt endpoint handling code stores the buffer pointer in the QH padding field. We need to make it the size of a pointer to avoid strict aliasing issue with the compiler. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * usb: ehci: Support interrupt transfers via periodic listPatrick Georgi2013-03-18-5/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupt transfers aren't meant to be used from the async list (the EHCI spec indicates trouble with low/full-speed intr on async). Build a periodic list instead, and provide an API to make use of it. Then, use that API from the existing interrupt transfer API. This provides support for USB keyboards using EHCI. Use timeouts to ensure we cannot get stuck in the keyboard scanning if something wrong happens (USB device unplugged or fatal I/O error) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * usb: ehci: exynos: Enable non-dt pathVivek Gautam2013-03-18-0/+7
| | | | | | | | | | | | | | | | Enabling the non-dt path for the driver so that we don't get any build errors for non-dt configuration. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * usb: ehci: exynos: Fix multiple FDT decodeVivek Gautam2013-03-18-28/+16
| | | | | | | | | | | | | | | | | | | | With current FDT support driver tries to parse device node twice in ehci_hcd_init() and ehci_hcd_stop(), which shouldn't happen ideally. Making provision to store data in a global structure and thereby passing its pointer when needed. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
generated by cgit v1.1 at 2024-12-20 19:06:42 +0000