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* ARM: zynq: Add reset-gpio property for USB on ZyboMichal Simek2016-02-22-1/+2
| | | | | | | | DTS syncup with Linux kernel. Add missing reset-gpio property. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: phy: realtek: Use generic genphy_parse_link() for RTL8211EMichal Simek2016-02-22-1/+9
| | | | | | | | | | | | | | | | | | | | The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which ending up in driver failure that link is not up. Log: Zynq> dhcp ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done ethernet@e000b000: No link. There is at least 1ms delay between spddone bit and link up. Use genphy_read_status() instead of realtek implemenation which is working with page 11. Linux driver is also using generic implementation. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Enable Realtek phys by defaultMichal Simek2016-02-22-0/+1
| | | | | | | This phy is available at Zybo board. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* i2c: spd: Extend SPD memory typesMichal Simek2016-02-22-1/+13
| | | | | | Decode DDR, DDR3 and DDR4 memories. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: ns16550: Add support for reg-offset propertyMichal Simek2016-02-22-2/+5
| | | | | | | | | | reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* zynq-common: Fix usbboot env variableJason Wu2016-02-22-2/+1
| | | | | | | Remove the miss-placed \0 and add missing ; for usbboot env variable. Signed-off-by: Jason Wu <jason.wu.misc@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Enable SPL RAM support by defaultMichal Simek2016-02-22-0/+1
| | | | | | | Use RAM support in jtagboot mode. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* ARM: zynq: Enable u-boot,dm-pre-reloc for qspiNathan Rossi2016-02-22-0/+3
| | | | | | | | | | Enable u-boot,dm-pre-reloc for qspi for zc706, zed and microzed. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* serial: zynq: Change logic in putcMichal Simek2016-02-22-2/+2
| | | | | | | | | | | | | | | | Sync logic with Linux kernel where TX empty flag is checked before char is sent. This logic is fixing problem with console on zynqmp platform. For example: DRAM: 2 GiB Enabling Caches... EL Level: �� sdhci@ff170000: 0 Using default environment Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* ARM: zynq: Remove ZYNQ_BOOT_FREEBSD optionMichal Simek2016-02-22-7/+1
| | | | | | | Remove CONFIG_ZYNQ_BOOT_FREEBSD configuration option and setup CONFIG_SYS_MMC_MAX_DEVICE 1 for all Zynq boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Read memory size setting from DTMichal Simek2016-02-22-16/+0
| | | | | | | OF_CONTROL is setup by default and memory reading is done via DT. Remove all config files with memory references. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mmc: Kconfig: Add Arasan SDHCI entryMichal Simek2016-02-22-20/+19
| | | | | | Add Arasan SDHCI entry to Kconfig and fix all references. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: zc770: Remove unused ifdefs for xm011 and xm013Michal Simek2016-02-22-4/+0
| | | | | | Clean config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Remove unused SPI base addressesMichal Simek2016-02-22-5/+0
| | | | | | | | Remove unused macros. Adresses are taken from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-21-57/+1506
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| * imx: mx7d: isolate resources to domain 0 for A7 corePeng Fan2016-02-21-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7dsabresd: add command and macros for boot m4 corePeng Fan2016-02-21-0/+24
| | | | | | | | | | | | | | | | Introduce macros and command to support booting M4 core for i.MX7D SabreSD board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6sxsabresd: add command and macros for boot m4 corePeng Fan2016-02-21-0/+24
| | | | | | | | | | | | | | | | Introduce macros and command to support booting M4 core for i.MX6SX SabreSD board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce boot auxiliary corePeng Fan2016-02-21-0/+79
| | | | | | | | | | | | | | | | | | | | | | To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000". Introduce Kconfig option IMX_BOOTAUX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: clock support for RDCPeng Fan2016-02-21-0/+6
| | | | | | | | | | | | If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: Add RDC supportPeng Fan2016-02-21-0/+182
| | | | | | | | | | | | | | | | Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6sx Add RDC mappings of masters and peripheralsPeng Fan2016-02-21-0/+159
| | | | | | | | | | | | | | Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce Resource Domain Controller supportPeng Fan2016-02-21-0/+304
| | | | | | | | | | | | | | | | | | Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: introduce rdc regsPeng Fan2016-02-21-0/+24
| | | | | | | | | | | | | | | | Introudce rdc regs structure and rdc sema reg structure for i.MX6. For now, to i.MX6, only i.MX6SX supports this. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6quq7: add sd card detectionJulien CORJON2016-02-21-0/+19
| | | | | | | | | | | | Add board_mmc_getcd function and declare CD_GPIO for SDCard. Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
| * imx: mx6quq7: specify max_bus_witdh directly in usdhc_cfgJulien CORJON2016-02-21-4/+2
| | | | | | | | | | | | | | Specify max_bus_width directly in usdhc_cfg static definition instead of tweaking it in the board_mmc_init() function. Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
| * imx: mx6quq7: fix USDHC4 declarationJulien CORJON2016-02-21-1/+1
| | | | | | | | | | | | | | | | USDHC2 does not exist on mx6quq7 board, as USDHC4 was already been declared this is probably a typo. Signed-off-by: Julien Corjon <corjon.j@ecagroup.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * board: tbs2910: Autoselect environment device when booting from SDSoeren Moch2016-02-21-2/+13
| | | | | | | | | | | | | | | | | | | | | | Implement board specific functions to select the environment device and partition when booting from SD/MMC. SD2: mmc 0 0 SD3: mmc 1 0 eMMC: mmc 2 1 Signed-off-by: Soeren Moch <smoch@web.de>
| * imx: mx6: Implement mmc_get_env_partSoeren Moch2016-02-21-3/+33
| | | | | | | | | | | | | | | | | | | | commit 216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by: Soeren Moch <smoch@web.de>
| * pinctrl: imx: Support i.MX7DPeng Fan2016-02-21-0/+56
| | | | | | | | | | | | | | | | | | | | | | Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pinctrl: imx: Introduce pinctrl driver for i.MX6Peng Fan2016-02-21-0/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas2016-02-21-23/+59
| | | | | | | | | | | | | | | | | | | | | | | | Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * mx7dsabresd: Make 'ums' command functionalFabio Estevam2016-02-21-23/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When running the 'ums' command we get: => ums 0 mmc 0 UMS: disk start sector: 0x0, count: 0xe18000 g_dnl_register: failed!, error: -22 ERROR: g_dnl_register failed at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage() Fix this by initializing USB OTG1 port as USB device mode instead of host. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7dsabresd: Use Adrian's NXP email addressFabio Estevam2016-02-21-1/+1
| | | | | | | | | | | | Use the new NXP email address for the board maintainer. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6ul_14x14_evk: Select CONFIG_FSL_QSPIFabio Estevam2016-02-21-0/+1
| | | | | | | | | | | | | | | | | | | | Select CONFIG_FSL_QSPI so that the SPI can be probed: => sf probe SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mxsboot: remove unused includeAndreas Bießmann2016-02-21-1/+0
| | | | | | | | | | | | | | | | | | | | Commit 276d3ebb883024d753cd9c69ab2fd243ffa1262e removed htole32() but missed to remove the corresponding header. This is annoying, since BSD systems do not have endian.h. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Michael Heimpold <mhei@heimpold.de>
* | x86: doc: Update to include Intel Bayley Bay board instructionsBin Meng2016-02-21-16/+20
| | | | | | | | | | | | | | | | | | | | | | Update existing documentation to mention Intel Bayley Bay board instructions, an additional Bay Trail based board to MinnowMax. This also adds a minor change to QEMU section to indicate clearly the instructions are for bare mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+298
| | | | | | | | | | | | | | | | | | This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng2016-02-21-1/+5
| | | | | | | | | | | | | | | | Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng2016-02-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
* | superio: Add SMSC SIO1007 driverBin Meng2016-02-21-0/+242
| | | | | | | | | | | | | | | | | | | | | | The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management. This adds a simple driver to enable serial port and handle GPIO. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: ivybridge: Add FSP supportBin Meng2016-02-21-0/+131
| | | | | | | | | | | | | | | | | | | | IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
* | x86: fix memalign() parameter orderStephen Warren2016-02-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Purely by code inspection, it looks like the parameter order to memalign() is swapped; its parameters are (align, size). 4096 is a likely desired alignment, and a variable named size sounds like a size:-) Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-20-602/+1573
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| * | vinco: add Maintainers fileAndreas Bießmann2016-02-20-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * | ARM: Add Support for the VInCo platformGregory CLEMENT2016-02-19-0/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatile Industrial Communication platform is a community oriented board from Landis + Gyr. It comes with: - an RS-485 port - 2 Ethernet ports - a wireless M-BUS - a 4G modem - a 4MB SPI flash - a 4GB eMMC Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> [rebase on current TOT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: sama5d2: configure the L2 cache memorySamuel Mescoff2016-02-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91: Add support for DENX MA5D4 SoM and EVKMarek Vasut2016-02-18-0/+709
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
generated by cgit v1.1 at 2024-12-22 22:48:33 +0000