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* usb: tegra: combine header fileStefan Agner2014-04-17-755/+225
| | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: tegra: fix PHY configurationStefan Agner2014-04-17-9/+27
| | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: tegra: fix USB2 powerdown for Tegra30 and laterStefan Agner2014-04-17-0/+3
| | | | | | | | | | | | Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register which brings USB2 in UTMI mode to work. This was clearly missing since the forced powerdown bit is set in reset by default for all USB ports. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: add Jetson TK1 boardStephen Warren2014-04-17-0/+428
| | | | | | | | Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of its design with Venice2. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-04-17-744/+706
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-04-17-753/+680
| | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Tegra30 pinmux cleanupStephen Warren2014-04-17-1151/+1082
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra30_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted one entry in pinmux-config-cardhu.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-412/+397
| | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinmux naming consistency fixesStephen Warren2014-04-17-217/+223
| | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: reduce public pinmux APIStephen Warren2014-04-17-8/+2
| | | | | | | | | | | Remove a few unused functions from the pinmux header. They aren't currently used, and removing them prevents any new usage from appearing. This will ease moving to just pinmux_config_table() and padgrp_config_table() in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove duplicationStephen Warren2014-04-17-2072/+732
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use apb_misc.h in more placesStephen Warren2014-04-17-8/+16
| | | | | | | | | | | | | | | | | Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: prototype pinmux_init() in board.hStephen Warren2014-04-17-11/+7
| | | | | | | | | pinmux_init() is a board-level function, not a pinmux driver function. Move the prototype to a board header rather than the driver header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20Stephen Warren2014-04-17-11/+10
| | | | | | | | | | | | | | | | | For consistency with other SoCs, modify Tegra20's enum pmux_func to: * Remove PMUX_FUNC values that aren't real * Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0; this will be assumed by pinmux_set_func() in a future patch. Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a private define inside the driver to prevent this from causing compilaton errors. This will be cleaned up when the pin tables are re-written in a later patch in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove vddioStephen Warren2014-04-17-86/+0
| | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove func_safeStephen Warren2014-04-17-24/+0
| | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* board:tricorder: fixup SPL OOB layoutAndreas Bießmann2014-04-11-5/+6
| | | | | | | | | | | Commit d016dc42cedbf6102e100fa9ecb58462edfb14f8 changed the layout of BCH8 SW on omap3 boards. We need to adopt the ecc layout for the nand_spl_simle driver to avoid wrong ecc errors. Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* board:tricorder: enable omap_gpio clocksAndreas Bießmann2014-04-11-0/+3
| | | | | | Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* board:tricorder: always work with valid eeprom dataAndreas Bießmann2014-04-11-0/+2
| | | | | | | | | | | | | Commit 890880583d84607e36b52a785a96b167728bbf73 introduced EEPROM parsing and board detection but faild to return a valid tricorder_eeprom struct for backup case. When pressing S200 while reading EEPROM we ignore the value. We returned falsely a tricorder_eeprom struct with uninitialized data which is just garbage. Initialize it by zeroing the whole structure. Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm:board:trats2:FIX: Clear INFORM4 and INFORM5 registers at correct bootŁukasz Majewski2014-04-11-0/+13
| | | | | | | | | | | | | | During switch to device tree, commit 1ecab0f has removed this code. INFORM4 and INFORM5 registers are used by TRATS2 first stage bootloader for providing recovery. For normal operation, those two must be cleared out. This error emerges when one force reset from u-boot's command line for three times. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* kbuild: fix a bug in regeneration of linker scriptsMasahiro Yamada2014-04-11-6/+6
| | | | | | | | | | | | | | | | | | | | | In some use cases, SPL linker script was not updated even when it should be. For instance, $ make tricoder_config all [ build complete ] ... modify include/configs/tricoder.h $ make spl/u-boot-spl.lds should be updated in this case, but it wasn't. To fix this problem, linker scripts generation should be handled by $(call if_changed_dep,...) rather than by $(call if_changed,...). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-08-7263/+5284
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
| * Revert "Start the deprecation process for generic board"Tom Rini2014-04-04-195/+0
| | | | | | | | | | | | | | | | | | We've run into a non-trivial conversion to CONFIG_SYS_GENERIC_BOARD so we'll postpone this notice until right after v2014.04 is out. This reverts commit 36c4b1d98059244c34ec3327d9cc9f3c552fd01b. Signed-off-by: Tom Rini <trini@ti.com>
| * trats/trats2: enable CONFIG_RANDOM_UUIDPrzemyslaw Marczak2014-04-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This change enables automatically uuid generation by command gpt. In case of updating partitions layout user don't need to care about generate uuid manually. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: trini@ti.com
| * cmd:gpt: randomly generate each partition uuid if undefinedPrzemyslaw Marczak2014-04-02-22/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: - randomly generate partition uuid if any is undefined and CONFIG_RAND_UUID is defined - print debug info about set/unset/generated uuid - update doc/README.gpt Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Tom Rini <trini@ti.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * new commands: uuid and guid - generate random unique identifierPrzemyslaw Marczak2014-04-02-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those commands basis on implementation of random UUID generator version 4 which is described in RFC4122. The same algorithm is used for generation both ids but string representation is different as below. char: 0 9 14 19 24 36 xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx UUID: be be be be be GUID: le le le be be Commands usage: - uuid [<varname>] - guid [<varname>] The result is saved in environment as a "varname" variable if argument is given, if not then it is printed. New config: - CONFIG_CMD_UUID Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: trini@ti.com
| * lib: uuid: add functions to generate UUID version 4Przemyslaw Marczak2014-04-02-5/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to generate UUID (Universally Unique Identifier) in version 4 based on RFC4122, which is randomly. Source: https://www.ietf.org/rfc/rfc4122.txt Changes: - new configs: - CONFIG_LIB_UUID for compile lib/uuid.c - CONFIG_RANDOM_UUID for functions gen_rand_uuid() and gen_rand_uuid_str() - add configs dependency to include/config_fallbacks.h for lib uuid. lib/uuid.c: - add gen_rand_uuid() - this function writes 16 bytes len binary representation of UUID v4 to the memory at given address. - add gen_rand_uuid_str() - this function writes 37 bytes len hexadecimal ASCII string representation of UUID v4 to the memory at given address. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com> [trini: Add CONFIG_EFI_PARTITION to fallbacks] Signed-off-by: Tom Rini <trini@ti.com>
| * lib: uuid: code refactor for proper maintain between uuid bin and stringPrzemyslaw Marczak2014-04-02-36/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes in lib/uuid.c to: - uuid_str_to_bin() - uuid_bin_to_str() New parameter is added to specify input/output string format in listed functions This change allows easy recognize which UUID type is or should be stored in given string array. Binary data of UUID and GUID is always stored in big endian, only string representations are different as follows. String byte: 0 36 String char: xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx string UUID: be be be be be string GUID: le le le be be This patch also updates functions calls and declarations in a whole code. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: trini@ti.com
| * part_efi: move uuid<->string conversion functions into lib/uuid.cPrzemyslaw Marczak2014-04-02-87/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces cleanup for uuid library. Changes: - move uuid<->string conversion functions into lib/uuid.c so they can be used by code outside part_efi.c. - rename uuid_string() to uuid_bin_to_str() for consistency with existing uuid_str_to_bin() - add an error return code to uuid_str_to_bin() - update existing code to the new library functions. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: trini@ti.com
| * ahci: Fix data abort on multiple scsi resets.Roger Quadros2014-04-02-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2faf5fb82ed6 introduced a regression that causes a data abort when running scsi init followed by scsi reset. There are 2 problems with the original commit 1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is assigned to ataid[port] and used by other functions. 2) The function ata_scsiop_inquiry() tries to free memory which was never allocated on the heap. Fix these problems by using tmpid as a temporary cache aligned buffer. Allocate memory separately for ataid[port] and re-use it if required. Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages) Reported-by: Eli Nidam <elini@marvell.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: fsl_esdhc: add controller reset in case of data related errors tooAndrew Gabbasov2014-04-02-27/+36
| | | | | | | | | | | | | | | | The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: fsl_esdhc: fix calculation of timeout for data transactionsAndrew Gabbasov2014-04-02-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: Add 'mmc rst-function' sub-commandTom Rini2014-04-02-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value in order for warm reset of the system to work. Details on this being required will be part of the eMMC datasheet. Also add using this command to the dra7xx README. * Whitespace fix by panto Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: sh_mmcif: Fix warning by unused variableNobuhiro Iwamatsu2014-04-02-2/+1
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: sh_mmcif: Fix compile errorNobuhiro Iwamatsu2014-04-02-1/+1
| | | | | | | | | | | | | | | | | | | | BY commit "mmc: Split mmc struct, rework mmc initialization (v2)", sh_mmcif has compile error. This fixes compile error. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Pantelis Antoniou <panto@antoniou-consulting.com> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * Prepare v2014.04-rc3Tom Rini2014-03-31-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * Kbuild: allow building tools without board configurationMasahiro Yamada2014-03-31-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Kbuild, U-Boot could build under tools/ directory withour configuring for a specific board. That feature was lost when switching to Kbuild. This patch revives it again by adding a make target "tools-only". Usage: $ make tools-only Neither board configuration nor cross compiler are required to build host tools. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
| * tegra: fix Makefile to pass per-file CFLAGSMasahiro Yamada2014-03-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since Kbuild was introduced, warmboot_avp.o has been compiled without -march=armv4t. Makefile should be adjusted to pass a per-file option. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2014-03-31-2/+2
| |\
| | * board: ecovec: fix USB0 clock enableBaruch Siach2014-03-31-1/+1
| | | | | | | | | | | | | | | | | | | | | Enable USB0 clock by resetting bit 20 of MSTPCR2. Leave other bits unchanged. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * board: ecovec: fix debug LEDs pin directionBaruch Siach2014-03-31-1/+1
| | | | | | | | | | | | | | | | | | | | | All pins should be output. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | drivers: i2c: delete an unused source fileMasahiro Yamada2014-03-31-387/+0
| |/ | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de>
| * blackfin: mmc: Correct mmc_host_is_spi and bfin_sdh.cTom Rini2014-03-28-2/+2
| | | | | | | | | | | | | | | | In the recent mmc cleanup, the mmc_host_is_spi macro was broken and bfin_sdh.c had mmc->bus_width turned into mmc_bus_width(mmc), both of which were incorrect. Signed-off-by: Tom Rini <trini@ti.com>
| * am335x_evm: Drop CONFIG_SPL_ETH_SUPPORT from default buildTom Rini2014-03-28-3/+0
| | | | | | | | | | | | | | | | On the boards this target supports this option is either non possible without hardware mods (Beaglebone White/Black) or not supported due to board design. Drop this and regain some space. Signed-off-by: Tom Rini <trini@ti.com>
| * am335x_evm: Clarify when we build board_eth_initTom Rini2014-03-28-2/+16
| | | | | | | | | | | | | | | | If we build this function in cases where we would be discarding it anyhow we still end up with maybe unused warnings. Rather than litter the function with __maybe_unused, just spell out when to build it. Signed-off-by: Tom Rini <trini@ti.com>
| * kbuild: fix bugs in cleaning targetsMasahiro Yamada2014-03-28-3/+4
| | | | | | | | | | | | | | | | | | "make clean", "make clobber", "make mrproper" and "make distclean" missed to clean-up some files when they were run with O=<some_dir> option. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: Wolfgang Denk <wd@denx.de>
| * kbuild: create a build directory automatically for out-of-tree buildMasahiro Yamada2014-03-28-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Kbuild, the build system created a build directory, when it did not exist, for out-of-tree build. This feature was dropped when we switched to Kbuild because many of lines in makefiles were copied from Linux Kernel. (In Linux Kernel, we have to create a build directory by ourselves before starting build.) That feature seems worth reviving for less typing even if our code and Linux Kernel diverge. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * Start the deprecation process for generic boardSimon Glass2014-03-28-0/+195
| | | | | | | | | | | | | | | | We should move forward to remove the old board init code. Add a prominent message to encourage maintainers to get started on this work. Signed-off-by: Simon Glass <sjg@chromium.org>
| * trats/trats2: enable exynos ace sha subsystem and hardware based lib randPrzemyslaw Marczak2014-03-28-0/+8
| | | | | | | | | | | | | | | | | | | | | | This allows to use exynos random number generator by enabling configs: - CONFIG_EXYNOS_ACE_SHA - CONFIG_LIB_HW_RAND Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> cc: Piotr Wilczek <p.wilczek@samsung.com> cc: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-12-24 13:46:18 +0000