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* zynqmp: Add support for EMMC bootmodeMichal Simek2015-04-29-1/+3
| | | | | | Add support for EMMC bootmode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: Add support for emulation platform - VeloceMichal Simek2015-04-29-2/+12
| | | | | | | Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: timer: Fix wrong timer calculationSiva Durga Prasad Paladugu2015-04-29-1/+3
| | | | | | | | | | Fix wrong timer calculation in get_timer_masked incase of overflow. This fixes the issue of getting wrong time from get_timer() calls. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: sdhci: Remove the quirk SDHCI_QUIRK_NO_CDSiva Durga Prasad Paladugu2015-04-29-1/+1
| | | | | | | | Remove the quirk SDHCI_QUIRK_NO_CD as it is not required. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: Add support for R5 sw loadingMichal Simek2015-04-29-3/+285
| | | | | | | Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* zynqmp: caches: Enable dcache for zynqmpSiva Durga Prasad Paladugu2015-04-29-1/+165
| | | | | | | | Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: slcr: Disable all level shiftersSiva Durga Prasad Paladugu2015-04-29-0/+7
| | | | | | | | | | | Disable all level shifters before enabling the PS-to-PL level shifters as it would be good to disable all level shifters before enabling the PS-to-PL in order to ensure that it is in proper state Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: drop legacy ps7_init.c/h supportMasahiro Yamada2015-04-29-7/+2
| | | | | | | | | | | | | | We are about to change the location for ps7_init files, breaking the current work-flows. It is good time to drop the legacy ps7_init.c/h support. Going forward, please use ps7_init_gpl.c/h all the time. If you are still using old Xilinx tools that are only able to generate ps7_init.c/h, rename them into ps7_init_gpl.c/h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Add Zynq PicoZed board supportNathan Rossi2015-04-29-0/+61
| | | | | | | | | | | | | | | | | | The PicoZed is a System-on-Module board which is marketed as part of the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000 processor. This patch adds support that covers all the variants of the PicoZed including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This patch set however only covers support for the System-on-Module and does not cover any extra components that are available on carrier boards (except those that are fanned out of the module itself). More information on this board, its variants and available carrier boards is available at: http://zedboard.org/product/picozed Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* serial: zynq: Add support for slow emulation platformMichal Simek2015-04-29-1/+7
| | | | | | | | On slow platforms not all baudrate setting is valid. Check it directly in the driver and setup maximum possible frequency. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Enable GPIO driver and GPIO commandsMichal Simek2015-04-29-0/+3
| | | | | | Enable GPIO driver and GPIO commands. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* gpio: add Xilinx Zynq PS GPIO driverAndrea Scian2015-04-29-0/+287
| | | | | | | | | Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-04-28-94/+93
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| * sf: Fix to compute proper sector_sizeJagannadha Sutradharudu Teki2015-04-28-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upto now flash sector_size is assigned from params which isn't necessarily a sector size from vendor, so based on the SECT_* flags from flash_params the erase_size will compute and it will become the sector_size finally. Bug report (from Bin Meng): => sf probe SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB, total 2 MiB, mapped at ffe00000 => sf erase 0 +100 SF: 65536 bytes @ 0x0 Erased: OK Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reported-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: sf: Make SST flash write op work againBin Meng2015-04-28-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | With SPI flash moving to driver model, commit fbb0991 "dm: Convert spi_flash_probe() and 'sf probe' to use driver model" ignored the SST flash-specific write op (byte program & word program), which actually broke the SST flash from wroking. This commit makes SST flash work again under driver model, by adding SST flash-specific handling in the spi_flash_std_write(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: Save flash flags to struct spi_flashBin Meng2015-04-28-0/+4
| | | | | | | | | | | | | | | | Add a new member 'flags' in struct spi_flash to store the flash flags during spi_flash_validate_params(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: omap3: Fix timeout handlingDavid Dueck2015-04-27-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timeout value is never reset during the transfer. This means that when transferring more data we eventually trigger the timeout. This was reported on the mailing list: "Spansion SPI flash read timeout with AM335x" Signed-off-by: David Dueck <davidcdueck@googlemail.com> CC: Tom Rini <trini@konsulko.com> CC: Stefan Roese <sr@denx.de> CC: Andy Pont <andy.pont@sdcsystems.com> Tested-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * Revert "spi: add config option to enable the WP pin function on st micron ↵Jagannadha Sutradharudu Teki2015-04-23-45/+0
| | | | | | | | | | | | | | | | | | | | | | | | flashes" This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Heiko Schocher <hs@denx.de>
| * dm: spi: Correct SPI claim/release_bus() methodsSimon Glass2015-04-23-12/+17
| | | | | | | | | | | | | | | | | | | | | | These methods should be passed a slave device, not a bus. This matches the old SPI interface. It is important to know which device is claiming the bus so passing a bus is not that useful. Reported-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * mtd: spi: check return value of spi_setup_slavePeng Fan2015-04-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to check value of spi_setup_slave and spi_setup_slave_fdt. If their return value 'bus' is NULL, there is no need to pass it to following spi_flash_probe_tail. If 'bus' is null, the original function flow is as following: spi_flash_probe |->spi_setup_slave |->spi_probe_bus_tail |->spi_flash_probe_slave |->spi_free_slave Alougth check the pointer in spi_free_slave is ok, checking the return value of spi_setup_slave and spi_setup_slave_fdt is better. Before this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! SF: Failed to set up slave data abort pc : [<fff66dcc>] lr : [<fff7628c>] reloc pc : [<87814dcc>] lr : [<8782428c>] sp : fdf4fcf0 ip : e630396c fp : fe0d0888 r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00 r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... " After this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! Failed to initialize SPI flash at 0:2 " No data abort using this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * cmd_sf: Fix problem with "sf update" and unaligned lengthStefan Roese2015-04-22-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SoCFPGA, using "sf update" with an non-4byte aligned length leads to a hangup (and reboot via watchdog). This is because of the unaligned access in the cadence QSPI driver which is hard to prevent since the data is written into a 4-byte wide FIFO. This patch fixes this problem by changing the behavior of the last sector write (not sector aligned). The new code is even simpler and copies the source data into the temp buffer and now uses the temp buffer to write the complete sector. So only one SPI sector write is used now instead of 2 in the old version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gerlando Falauto <gerlando.falauto@keymile.com> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Holger Brunck <holger.brunck@keymile.com> Acked-by: Gerlando Falauto <gerlando.falauto@keymile.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi flash: fix trivial problemsPavel Machek2015-04-22-5/+3
| | | | | | | | | | | | | | | | Fix typos and too big #ifdef. Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * zynq: spi: Remove unnecessary error conditionSiva Durga Prasad Paladugu2015-04-22-3/+0
| | | | | | | | | | | | | | | | | | | | Removed the unnecessary error check from spi_xfer as the bitlen zero is possible now to deassert the chip select for which no data is required to be transfered. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Poll both the read status and flag statusSiva Durga Prasad Paladugu2015-04-22-7/+25
| | | | | | | | | | | | | | | | | | Poll both the Read status and Flag status registers for sucessful erase and program operations for the Micron devices with E_FSR flag set in params table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Correct the macros as per new array fast read commandSiva Durga Prasad Paladugu2015-04-22-5/+6
| | | | | | | | | | | | | | | | | | Correct the macros as per insertion of array fast read command CMD_READ_ARRAY_FAST in spi_read_cmds_array in file sf_probe.c Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2015-04-24-3/+22
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| * | fdt: Fix handling of paths with options in themHans de Goede2015-04-23-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi builds would no longer boot. The problem is that stdout-path is now set like this in the upstream dts files: stdout-path = "serial0:115200n8". The use of options in of-paths, either after an alias name, or after a full path, e.g. stdout-path = "/soc@01c00000/serial@01c28000:115200", is standard of usage, but something which the u-boot dts code so far did not handle. This commit fixes this, adding support for both path formats. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-04-24-7/+8
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| * | | MIPS: implement device-tree handover to Linux kernelDaniel Schwierzeck2015-04-24-7/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device-tree handover to Linux kernel conforming with MIPS UHI [1]. Register $a0 will be set to the reserved value -2. The address of the device-tree blob will be stored as KSEG0 address in $a1. $a2 and $a3 are set to zero. [1] http://prplfoundation.org/wiki/MIPS_documentation Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-713/+11694
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| * | armv8/fsl-lsch3: Implement workaround for I2C erratum A009203York Sun2015-04-23-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
| * | ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu2015-04-23-6/+88
| | | | | | | | | | | | | | | | | | | | | This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085ardb: Enable NAND SPL supportScott Wood2015-04-23-5/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | freescale/qixis: Add support for booting from NANDScott Wood2015-04-23-10/+21
| | | | | | | | | | | | | | | | | | | | | Use "qixis_reset nand" to reset the board to boot from NAND. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-8/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-71/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/ls2085qds: Add support ethernetPrabhakar Kushwaha2015-04-23-13/+488
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun2015-04-23-2/+975
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun2015-04-23-15/+1148
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | driver/ldpaa: Add support of WRIOP static data structurePrabhakar Kushwaha2015-04-23-6/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-ch3: Add support to print RCW configurationBhupesh Sharma2015-04-23-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | net/memac_phy: reuse driver for little endian SoCsShaohui Xie2015-04-23-24/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memac for PHY management on little endian SoCs is similar on big endian SoCs, so we modify the driver by using I/O accessor function to handle the endianness, so the driver can be reused on little endian SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access is little endian, if not, the I/O access is big endian. Move fsl_memac.h out of powerpc include. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | drivers/fsl-mc: Changed MC firmware loading for new boot architectureJ. German Rivera2015-04-23-131/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | net/phy/cortina: Fix compilation warningpankaj chauhan2015-04-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix comilation warning which is emitted when firmware address is more than 32 bit. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8: Add SerDes framework for Layerscape ArchitectureMinghuan Lian2015-04-23-0/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/ldpaa_eth: Update ldpaa ethernet driverPrabhakar Kushwaha2015-04-23-24/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix flush_dcache_range() input parameter to use start and end addresses. Change ethernet interface name to DPNI. Update entry criteria for ldpaa_eth_stop. Ethernet stack first stop the device before performing next operation. At the time of Ethernet driver registration, net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as ETH_STATE_INIT in ldpaa_eth_stop. Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does not support PHYLIB. Instead of clearing pull descriptor one time, clear it before issuing any volatile dequeue command. Volatile command does not return frame immidiately, wait till a frame is available in DQRR. This frame can be valid or expired. Flush buffer before releasing to BMan ensure the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Use correct compatible for serial clock fixupScott Wood2015-04-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085a: Add workaround for USB erratum A-008751Scott Wood2015-04-23-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | fsl-lsch3: Introduce place for common early SoC initScott Wood2015-04-23-2/+25
| | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Update early MMU tableYork Sun2015-04-23-17/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During booting, IFC is mapped to low region. After booting up, IFC is remapped to high region for larger space. The environmental variables are also stored at high region. In order to read the variables during booting, a virtual mapping is required. Cache was enabled for entire IFC space before. Actually the first two entries are big enough (4MB) to cover the boot code and environmental variables. Remove extra entries. Move OCRAM entry out of ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2025-01-02 08:32:12 +0000