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* sunxi: Add Marsboard A10 supportAleksei Mamlin2015-01-22-0/+14
| | | | | | | | | | | | | | This patch add support for Marsboard A10 board. The Marsboard A10 is a A10 based development board with 1G RAM, 1G NAND, micro SD card slot, SATA 2.0 socket, 10/100 ethernet, mini HDMI port, 1 USB OTG port and 2 USB 2.0 ports. Board does not use the AXP209 pmic, it does not have a pmic at all. Board also have 2 expansion 70 pin headers. Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* video: ssd2828: Allow using 'pclk' as the PLL clock sourceSiarhei Siamashka2015-01-22-7/+28
| | | | | | | | | | | | | | | | | | | Instead of using the internal 'tx_clk' clock source, it is also possible to use the pixel clock signal from the parallel LCD interface ('pclk') as the reference clock for PLL. The 'tx_clk' clock speed may be different on different boards/devices (the allowed range is 8MHz - 30MHz). Which is not very convenient, especially considering the need to know the exact 'tx_clk' clock speed. This clock speed may be difficult to identify without having device schematics and/or accurate documentation/sources every time. Using 'pclk' is free from all these problems. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sun6i: Add LCD display support for MSI Primo81 tabletSiarhei Siamashka2015-01-22-0/+10
| | | | | | | | | | | | | The MSI Primo81 tablet has B079XAN01/LP079X01 7.85" 768x1024 IPS MIPI display, connected to the parallel LCD interface via SSD2828 bridge chip. The panel has 18-bit color depth and needs dithering, in spite of having RGB data delivered from A31s to SSD2828 using 24-bit arrangement. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* video: sunxi: Hook up SSD2828 with the sunxi video driverSiarhei Siamashka2015-01-22-0/+45
| | | | | | | | | | Convert GPIO names from Kconfig strings into pin numbers for the 'ssd2828_config' struct. Add SSD2828 initialization between enabling the parallel LCD interface and turning on the backlight. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* video: Add support for SSD2828 (parallel LCD to MIPI bridge)Siarhei Siamashka2015-01-22-0/+616
| | | | | | | | | | | | | | | | | | | SSD2828 can take pixel data coming from a parallel LCD interface and translate it on the fly into MIPI DSI interface for driving a MIPI compatible TFT display. SSD2828 is configured over SPI interface, which may or may not have MISO pin wired up on some hardware. So a write-only SPI mode also has to be supported. The SSD2828 support code is implemented as a utility function and needs to be called from real display drivers, which are responsible for driving parallel LCD hardware in front of the video pipeline. The usage instructions are provided as comments in the header file. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* include: Add header file with MIPI DSI constants from linux 3.18Siarhei Siamashka2015-01-22-0/+130
| | | | | | | | | | | | The file, originally named "include/video/mipi_display.h", is taken from linux 3.18 (commit b2776bf7149bddd1f4161f14f79520f17fc1d71d). It provides MIPI DSI constants for DCS commands, which are needed to implement support for SSD2828 in u-boot. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: axp221: Add ELDO[1-3] supportSiarhei Siamashka2015-01-22-0/+51
| | | | | | | | | | | | | | | | | | And also add Kconfig option for selecting ELDO3 voltage. The reason for having this option is that the Android kernel sets ELDO3 to 1.2V when powering up LCD in the case if 'lcd_if' configuration variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely to supply power for a SSD2828 chip. However on the MSI Primo81 tablet, which is using this particular 'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to be unnecessary and it works regardless. Having no schematics of this tablet, I can only guess that 1.2V is supplied to SSD2828 in some other way. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add mk802_a10s board / defconfigHans de Goede2015-01-22-0/+48
| | | | | | | | | | | | | The mk802_a10s re-uses is the "classic" mk802 case and functionality, but has an A10s SoC inside rather then the A10, it features 512M or 1G RAM, 4G nand, a mini-hdmi female connector, USB-A receptacle, mini-usb receptacle (OTG) and a sdio realtek wifi chip. Unlike the original mk802 it does have a pmic, the axp152. For more details see: http://linux-sunxi.org/Semitime_g2 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add mk802ii board / defconfigHans de Goede2015-01-22-0/+10
| | | | | | | | | | | The mk802ii is a revised version of the mk802 A10 based hdmi tv-stick, it features 1G RAM, 4G nand, a hdmi male connector, USB-A receptacle, 2 micro usb receptacles (OTG & power) and USB-wifi, and does come with an axp209 pmic. For more details see: http://linux-sunxi.org/Rikomagic_mk802ii Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add mk802 board / defconfigHans de Goede2015-01-22-0/+11
| | | | | | | | | | | | The mk802 is the "classic" Allwinner A10 based hdmi tv-stick, it features 512M or 1G RAM, 4G nand, a mini-hdmi female connector, USB-A receptacle, mini-usb receptacle (OTG) and USB-wifi. Somewhat unique the mk802 does not use the AXP209 pmic, it does not have a pmic at all. For more details see: http://linux-sunxi.org/Rikomagic_mk802 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Remove CONFIG_TARGET_FOO for sun4i, sun6i and sun8i boardsHans de Goede2015-01-22-64/+9
| | | | | | | | | | CONFIG_TARGET_FOO is only used in board/sunxi/Makefile to select the dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some special handling of the bananapi/bananapro (both sun7i), iow it is not used at all on any sun4i, sun6i and sun8i boards so lets get rid of it there. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Convert sun4i boards to use auto dram configurationHans de Goede2015-01-22-99/+10
| | | | | | | | | | | | Currently we've separate detailed dram settings for all sun4i boards, this moves them over to using auto dram configuration so that we can get rid of all the per board dram_foo.c files. Tested-by: Hans de Goede <hdegoede@redhat.com> on a A10-OLinuXino-Lime, Chuwi_V7_CW0825 and ba10_tv_box Tested-by: Zoltan HERPAI <wigyori@uid0.hu> on a pcduino Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Stop differentiating between 512M and 1G variants of the same boardHans de Goede2015-01-22-142/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | While working on adding more boards I noticed that we lack a config for the 512M cubieboard, and that some of the new boards which I want to add also have 512M and 1G variants, rather then adding 2 defconfig's for all of these, lets switch the exising boards which have both a 512M and 1024M variant over to the sun4i dram autoconfig code. This also drops the foo_RAMSIZE_defconfig variants of boards where we currently have 2 separate configs already. Note: 1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with a value other then its default for now, but we need this to be configurable to support some new boards with auto dram config. 2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match the defaults, this is done to make it more clear what values are used for a certain board. This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G variants, the dram autoconfig code has also been tested on a 512M mk802 (a defconfig for the mk802 is added in a later patch). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: ba10_tv_box_defconfig: Fix USB not workingHans de Goede2015-01-22-1/+1
| | | | | | | PH12 is Vbus enable for Vbus2, not Vbus1. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp209: Disable interrupts when intializing the axp209Hans de Goede2015-01-22-1/+13
| | | | | | | | | | We do not use the axp209 interrupt, and at least in my mini-x (which does not have a power button) the pwr-button pin and the irq pin are soldered together, so if the axp209 keeps it irq asserted too long it will see a 10s pwr-button press and hard power off the board, disabling the irqs fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mmc: Add support for sun9i (A80)Hans de Goede2015-01-22-4/+20
| | | | | | | The clocks on the A80 are hooked up slightly different, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mmc: Use a realistic timeout when sending a mmc commandHans de Goede2015-01-22-1/+1
| | | | | | | | Wait 1 second for the sdcard to respond, rather then waiting for 0xfffff milliseconds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun9i: Add sun9i (A80) clock setup supportHans de Goede2015-01-22-0/+69
| | | | | | | | Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun9i: Add clock_sun9i.h with ccu register layout for sun9iHans de Goede2015-01-22-0/+141
| | | | | | | Add a headerfile with the sun9i ccu register layout. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun9i: Add cpu_sun9i.h with iomem definesHans de Goede2015-01-22-0/+112
| | | | | | | Add a headerfile with all the base addresses from the sun9i blocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Rename cpu.h to cpu_sun4i.hHans de Goede2015-01-22-145/+157
| | | | | | | | | sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite different, so add a wrapper cpu.h which includes the right mach specific cpu_sun#i.h based on mach, like we already do with clock.h and dram.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headersHans de Goede2015-01-22-4/+12
| | | | | | | | | | | Which pll-s are available depends on the machine type, move the clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files so that we only declare what is actually available. e.g. clock_get_pll5p() is not available on sun6i / sun8i, and with sun9i we get a completely different set of plls. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Drop pll6 setting from clock_init_uartHans de Goede2015-01-22-4/+1
| | | | | | | | As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: display: Make lcd display clk phase configurableHans de Goede2015-01-22-9/+12
| | | | | | | | | | | | | | | | | | | | While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup. This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value. This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit. The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Restore lowlevel_init usageHans de Goede2015-01-21-22/+21
| | | | | | | | | | | | | | | | | | 2 recent sunxi changes have removed the usage of lowlevel_init by moving some code around and then setting CONFIG_SKIP_LOWLEVEL_INIT. This is problematic for 2 reasons: 1) It does not just stop s_init from being called, it also stops cpu_init_cp15 from getting called, which is undesirable. 2) We want u-boot.bin to be usable standalone, without SPL, some people e.g. use an upstream u-boot.bin together with Allwinner's boot0 loader. So u-boot.bin must (re)initialize the gpios, timer, etc. This commit restores the lowlevel_init / s_init usage, while keeping the changes to no longer use the global-data (gd) struct in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge git://git.denx.de/u-boot-arcTom Rini2015-01-20-71/+123
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| * arc: rename "arc700" in "arcv1"Alexey Brodkin2015-01-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As a preparation to ARCv2 port submission we rename "arc700" folder to "arcv1" which stands for ARCv1 ISA also known as ARCompact. This will allow us to add more flavours of binary-compatible ARCv1 CPUs like ARC600 if needed later on and all required ARCv2 CPUs (which are binary incompatible with ARCv1) in "arcv2" folder in subsequent commits. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * board/synopsys: remove selection of CPU from the boardAlexey Brodkin2015-01-15-9/+3
| | | | | | | | | | | | | | | | Both ARCangel4 and AXS10x are FPGA-based boards so they may have different CPUs. For now we have only 1 option (ARC700) and we define this as default in arch Kconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: move common sources in libraryAlexey Brodkin2015-01-15-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * arc: move linker script in arch/arc/cpu folderAlexey Brodkin2015-01-15-0/+0
| | | | | | | | | | | | This way we'll be able to use the same one script for either ARC CPU. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: relocate - minor refactoring and clean-upAlexey Brodkin2015-01-15-11/+5
| | | | | | | | | | | | | | | | | | | | * use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: introduce separate section for interrupt vector tableIgor Guryanov2015-01-15-31/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * arc: add dependences on MMU presenceAlexey Brodkin2015-01-15-4/+18
| | | | | | | | | | | | | | | | | | Depending on MMU presence in CPU there're differences in HW behavior. For example address of instruction that caused exception is put in ECR register if MMU exists and in ERET register otherwise. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * arc: interrupts - fix mask setupIgor Guryanov2015-01-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | To disable interrupts we need to reset corresponding flags in STATUS32 register. For this we need to OR flags for interrupts level1 and level2 and then AND with current value in STATUS32. Before that implementation was incorrect. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * arc: add ECR (exception cause register) outputIgor Guryanov2015-01-15-4/+7
| | | | | | | | | | | | | | | | | | | | | | Exception cause register (ECR) contains value that describes a reason for exception that has happened. This helps a lot to figure-out what went wrong. Now we print this register contents when dumping registers. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
| * arc: check caches existence before useIgor Guryanov2015-01-15-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some cache operations ({i|d}cache_{enable|disable|status} or flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF is set. This is required for force disable of caches on early boot. What if something was executed before U-boot and enabled caches (low-level bootloaders, previously run kernel etc.)? But if CPU doesn't really have caches any attempt to access cache-related AUX registers triggers instruction error exception. So for convenience we'll try to avoid exceptions by checking if CPU actually has caches (we check separately data and instruction cache existence) at all. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-01-20-27/+1427
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| * | mmc: Skip changing bus width for MMC cards earlier than version 4.0Andrew Gabbasov2015-01-19-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wider bus widths (larger than default 1 bit) appeared in MMC standard version 4.0. So, for MMC cards of any earlier version trying to change the bus width (including ext_csd comparison) does not make any sense. It may work incorrectly and at least cause unnecessary timeouts. So, just skip the entire bus width related activity for earlier versions. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | mmc: Avoid redundant switching to 1-bit bus width for MMC cardsAndrew Gabbasov2015-01-19-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If all the commands switching an MMC card to 4- or 8-bit bus width fail, and the bus width for the controller and the driver is still set to default 1 bit, there is no need to send one more command to switch the card to 1-bit bus width. Also, if the card or host controller do not support wider bus widths, there is no need to send a switch command at all. However, if one of switch commands succeeds, but the subsequent ext_csd fields comparison fails, the card should be switched to some other bus width (next in the list for the loop), or to default 1-bit bus width as a last resort. That's why it would be incorrect to just remove the 1-bit bus width case from the list, it should still be processed in some cases. panto: Minor cosmetic edit removing superfluous parentheses. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
| * | mmc: extend mmcinfo output to show partition write reliability settingsDiego Santa Cruz2015-01-19-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the mmcinfo hardware partition info output to show partitions with write reliability enabled with the "WRREL" string. If the partition does not have write reliability enabled the "WRREL" string is omitted; this is analogous to the ehhanced attribute. Example output: Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.41 High Capacity: Yes Capacity: 13.8 GiB Bus Width: 4-bit Erase Group Size: 8 MiB HC WP Group Size: 16 MiB User Capacity: 13.8 GiB ENH WRREL User Enhanced Start: 0 Bytes User Enhanced Size: 512 MiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 64 MiB ENH WRREL GP2 Capacity: 64 MiB ENH WRREL Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: extend the mmc hwpartition sub-command to change write reliabilityDiego Santa Cruz2015-01-19-24/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change extends the mmc hwpartition sub-command to change the per-partition write reliability settings. It also changes the syntax used for the enhanced user data area slightly to better accomodate the write reliability option. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: extend the mmc hardware partitioning API with write reliabilityDiego Santa Cruz2015-01-19-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC partition write reliability settings are to be set while partitioning a device, as per the eMMC spec, so changes to these attributes needs to be done in the hardware partitioning API. This commit adds such support. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: add mmc hwpartition sub-command to do eMMC hardware partitioningDiego Santa Cruz2015-01-19-1/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the mmc hwpartition sub-command to perform eMMC hardware partitioning on an mmc device. The number of arguments can be large for a complex partitioning, but as the partitioning has to be done in one go it is difficult to make it simpler. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: add API to do eMMC hardware partitioningDiego Santa Cruz2015-01-19-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an API to do hardware partitioning on eMMC devices. The new mmc_hwpart_config() function does the partitioning in one go. As the different attributes and partitioning options on eMMC may be interdependent validation has to be done based on the complete partitioning configuration. The function accepts three modes: - MMC_HWPART_CONF_CHECK: just validates that the configuration is valid. - MMC_HWPART_CONF_SET: validates and sets all the fields in EXT_CSD but without setting the "partitioning completed" bit, and thus is reversible. - MMC_HWPART_CONF_COMPLETE: does everything and is thus not reversible. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: the ext_csd data may be used during init even if reading failedDiego Santa Cruz2015-01-19-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc_startup() function uses the ext_csd data even if reading it from the mmc device failed. This bug was introduced in commit bc897b1d4d86597311430dbe7b3e6c807c8c53e5. We now bail out if reading it fails, this should not be a problem as ext_csd was introduced in MMC 4.0 and this code is conditional on MMC >= 4.0. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: eMMC partitioning data is not effective till partitioning completedDiego Santa Cruz2015-01-19-23/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC spec says that partitioning is only effective after the PARTITION_SETTING_COMPLETED is set in EXT_CSD (and a power cycle was done, but that we cannot know). Thus the partition sizes and attributes should be ignored when that bit is not set, otherwise the various capacities are not coherent (e.g., the user data capacity will be that of the unpartitioned device while partition sizes would be non-zero). Prescence of non-zero partitioning data is nevertheless still used to activate the high-capacity size definitions (EXT_CSD_ERASE_GROUP_DEF) as it is necessary to set that to write any of the partitioning fields in EXT_CSD, so having partitioning data means someone previously activated that and we should keep it activated. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: show the erase group size and HC WP group size in mmcinfo outputDiego Santa Cruz2015-01-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the erase group size and high-capacity WP group size to mmcinfo's output. The erase group size is necessary to properly align erase requests on eMMC. The high-capacity WP group size is necessary to properly align partitions on eMMC. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: read the high capacity WP group size for eMMCDiego Santa Cruz2015-01-19-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Read the eMMC high capacity write protect group size at mmc device initialization. This is useful to correctly partition an eMMC device, as partitions need to be aligned to this size. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: fix erase_grp_size computation with high-capacity size definitionDiego Santa Cruz2015-01-19-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The erase_grp_size in struct mmc is to be a size in 512-byte sectors but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is enabled computed it as bytes, leading to erase sizes and alignment much larger than what is actually required by the mmc device. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | mmc: display size and start of eMMC enhanced user data area in mmcinfoDiego Santa Cruz2015-01-19-3/+8
| | | | | | | | | | | | | | | | | | | | | This adds output to show the eMMC enhanced user data area size and offset along with the partition sizes in mmcinfo's output. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
generated by cgit v1.1 at 2024-12-23 19:04:19 +0000