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* MA-7875-2 Support fastboot lock/unlock in i.MX6 platformWang Haoran2016-07-21-0/+45
| | | | | | | | | | | Enable fastboot lock/unlock support for Android in i.MX6 platform include: o i.MX6QP/Q/DL sabresd o i.MX6QP/Q/DL sabreauto (non NAND) o i.MX6SX sabresd o i.MX6SX sabreauto (nan NAND) Signed-off-by: Wang Haoran <Haoran.Wang@freescale.com>
* MA-7875-1 Support fastboot lock&unlock in u-bootWang Haoran2016-07-21-5/+602
| | | | | | | | | Support "fastboot flashing/oem lock/unlock" command. Support "fastboot getvar secure/unlocked" command. Protect the lock/unlock status by CAAM-Keyblob. Signed-off-by: Wang Haoran <Haoran.Wang@freescale.com>
* MA-7875 Enable CAAM for i.MX6Wang Haoran2016-07-21-0/+1044
| | | | | | | | | Cherry-pick patch from Renato Frias <b13784@freescale.com> to enable CAAM in U-Boot. Modify the CAAM Keyblob to general memory mode. Signed-off-by: Wang Haoran <Haoran.Wang@freescale.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12875 imx: mx7d_12x12_ddr3_arm2: enable NET utilitiesPeter Chen2016-06-02-1/+5
| | | | | | | Although the ethernet function is not ready for this board, the USB ethernet is ok, it can use NET utilities like DHCP using USB ethernet. Signed-off-by: Peter Chen <peter.chen@nxp.com>
* MLK-12865 Nand: Fix BCH debug1 register access issueYe Li2016-05-31-1/+1
| | | | | | Should have "&" to access the register address, otherwise uboot will hang. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-18-1/+8
| | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com>
* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1f0bb3940876c9b0be6f3c5fc320dde81ced4d97)
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
* imx: iomux-v3: fix UART input selectsStefan Agner2016-05-10-4/+4
| | | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2. From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit ee6717667799d70a42f00ba46d96f3f34c78f497)
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-16/+16
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2016-05-08-2/+24
| | | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0)
* MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrectable errorPeng Fan2016-05-07-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is porting from linux: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768 " We may meet the bitflips in reading an erased page(contains all 0xFF), this may causes the UBIFS corrupt, please see the log from Elie: ----------------------------------------------------------------- [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes ... [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815 [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383 [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383 ----------------------------------------------------------------- This patch does a check for the uncorrectable failure in the following steps: [0] set the threshold. The threshold is set based on the truth: "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH do the ECC." For the sake of safe, we will set the threshold with half the gf_len, and do not make it bigger the ECC strength. [1] count the bitflips of the current ECC chunk, assume it is N. [2] if the (N <= threshold) is true, we continue to read out the page with ECC disabled. and we count the bitflips again, assume it is N2. (We read out the whole page, not just a chunk, this makes the check more strictly, and make the code more simple.) [3] if the (N2 <= threshold) is true again, we can regard this is a erased page. This is because a real erased page is full of 0xFF(maybe also has several bitflips), while a page contains the 0xFF data will definitely has many bitflips in the ECC parity areas. [4] if the [3] fails, we can regard this is a page filled with the '0xFF' data. " Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit ceb324a2914487aa517a6c70a06a20b5e3438fda)
* imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-07-1/+1
| | | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch> (cherry picked from commit 8183b60202754d9d33ac1a2a68a5cc2cc4640fc6)
* MLK-12723 imx: Change the env offset on NAND to 60MYe Li2016-05-05-14/+14
| | | | | | | | | | | | | | | Current environment offset on NAND is 37MB, this will cause a alignment issue when erasing if nand erase block is 2MB. The saveenv is failed. => saveenv Saving Environment to NAND... Erasing NAND... Attempt to erase non block-aligned data Since the max erase block we supported is 4MB, adjust the env offset to 60MB, where is the last 4MB in 64MB reserved area for boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12629-2: i.MX6QP: update pluginPeng Fan2016-05-04-0/+12
| | | | | | | For i.MX6QP, the QoS settings is different from others. Align with DCD. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8a7d61d0731725c6f79488e0089b0b5bd35d028a)
* MLK-12736-2 mx6ulevk: Delete obsoleted android build target for old ddrYe Li2016-04-29-5/+0
| | | | | | | Remove the build target mx6ul_14x14_evk_ddr_eol_android_defconfig for the old ddr which is end of life. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12736 mx6ulevk: Delete obsoleted android build targetYe Li2016-04-29-5/+0
| | | | | | | The build target mx6ul_14x14_evk_android_defconfig is obsoleted. It is replaced by mx6ul_14x14_evk_brillo_defconfig. So remove this old file. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12705-2 imx7d: add build target for TO1.1Anson Huang2016-04-27-6/+6
| | | | | | | Default build target supports TO1.0 and TO1.2, TO1.1 uses its own defconfig. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-27-59/+59
| | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12691 mx6ullarm2: Add build targets for various boot devicesYe Li2016-04-21-0/+36
| | | | | | Four build targets added for eMMC, NAND, QSPIA and SPINOR boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+11
| | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12658 imx: adjust POR_B setting on i.MX6ULLAnson Huang2016-04-15-0/+13
| | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MA-7633-1 [Android-SD-EMMC] enable BCB partition in androidzhang sanshan2016-04-14-220/+384
| | | | | | | | 1 Add some APIs to operate BCB/command. 2 Add action to check the command of BCB. It can cover the case that power down when do factory-reset\ota in recovery mode. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MLK-12628 imx: mx6sx: enable MXC_CCM_CCGR3_LDB_DI0_OFFSETPeng Fan2016-04-12-3/+3
| | | | | | | MXC_CCM_CCGR3_LDB_DI0_OFFSET should not be disabled for i.MX6SX. Otherwise met compile error. And Discard the if else. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12616-11 imx: mx6ull: add mx6ull arm2 board supportPeng Fan2016-04-12-1/+1309
| | | | | | | | | | | | Support mx6ull ddr3 arm2 board. DDR script version 1.1. Passed memtester on 3 boards. Take mx6ul 14x14 ddr3 arm2 as reference. Note: LCD/NAND/ECSPI not tested, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12616-10 mx6ull: Add AIPS3 initializationYe Li2016-04-12-3/+3
| | | | | | Since the mx6ull adds the AIPS3, so enable its initialization. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-9 mx6ull: Update memory map addressYe Li2016-04-12-2/+16
| | | | | | | Update memory map address for mx6ull which uses AIPS3 and adjust UART8 to AIPS3 by replacing for ESAI. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-8 mx6ull: update CCM registers and clock settingsYe Li2016-04-12-32/+84
| | | | | | Update CCM registers and clock settings according the mx6ull changes Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-7 mx6ull: Not apply the PMIC_STBY_REQ_PAD work around for mx6ullPeng Fan2016-04-12-1/+1
| | | | | | Since the work around is only for mx6ul TO1.0, so not use it for mx6ull. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12616-6 mx6ull: Update s_init to skip pfd resetYe Li2016-04-12-2/+3
| | | | | | | The PFD reset is not needed for mx6ull, since it uses runtime cpu id checking here, add codes to skip it. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-5 GPT: Update GPT driver for MX6ULLYe Li2016-04-12-4/+5
| | | | | | | The MX6ULL has GPT with supporting OSC clock source, update the driver accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-4 OCOTP: Update driver for mx6ullPeng Fan2016-04-12-5/+38
| | | | | | | | | The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other banks use 256 bits. So we have to adjust the word and bank index when accessing the bank 8. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12616-3 mx6ull: Enable CONFIG_MX6UL definition for MX6ULLYe Li2016-04-12-0/+4
| | | | | | | | | Since iMX6ULL is derivative of iMX6UL, most of design are same, so enable CONFIG_MX6UL to reduce duplicated effort. We can use CONFIG_MX6ULL for the difference between these two chips. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-2 mx6ull: add MX6ULL major CPU TypeYe Li2016-04-12-2/+5
| | | | | | Add MXC_CPU_MX6ULL for i.MX6ULL CPU ID Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12616-1 mx6ull: Add iomux header fileYe Li2016-04-12-1/+1065
| | | | | | Add iomux headers according the file SDK_IOMaps_i.MX6ULL_Headers_b151218.zip Signed-off-by: Ye Li <ye.li@nxp.com>
* MA-7373 - [brillo]: store slot meta data in a raw partition, no file system.fang hui2016-04-11-105/+266
| | | | | | | | | | | | | | | Partition name change from slotmeta to misc. Read/write raw data on partition misc, not use ext4 file system. Store meta in bootloader_message.slot_suffix, as defined in bootable/recovery/bootloader.h The first 4 bytes of boot_ctl are defined as magic number. Also, modify code to remove warning in drivers/usb/gadget/bootctrl.c warning: implicit declaration of function 'do_read' Signed-off-by: fang hui <b31070@freescale.com>
* MA-7251 - [evk_6ul]: Support boot conctrol for brillofang hui2016-04-11-26/+566
| | | | | | | | | brillo need bootlader support boot control. bootlader can choose which slot(partition) to boot based on it's tactic. The commit support boot control for evk6ul Signed-off-by: fang hui <hui.fang@nxp.com>
* MLK-12603: mtd: gpmi: may use legacy bch geometry in u-bootHan Xu2016-03-29-1/+7
| | | | | | | | | provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy bch geometry. NOTICE: the feature must be enabled/disabled in both u-boot and kernel. Signed-off-by: Han Xu <han.xu@nxp.com>
* MLK-12576 imx: imx6ul: disable POR_B internal pull upAnson Huang2016-03-24-0/+9
| | | | | | | | | From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12563: imx: mx6ul evk: fix LCD_nPWREN settingPeng Fan2016-03-15-1/+1
| | | | | | | Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12551: imx6ul evk: fix 74LV OE usagePeng Fan2016-03-15-7/+1
| | | | | | | | | | | Fix 74LV OE gpio index. pinmux is correct, but gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW, but not high. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12492-2 ecspi: Add ecspi fuse module check only for MX6m6.0.1_1.0.0-gaYe Li2016-03-04-0/+2
| | | | | | | Need the CONFIG_MX6 for using the mx6_ecspi_fused funtion, otherwise will break build for other platforms like MX7. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12492-1 mx6: fix type style problems introduced by patch MLK-12483Ye Li2016-03-04-105/+106
| | | | | | | Some type style problems found by review-commits for previous patch MLK-12483, fix them in this patch and re-check. Signed-off-by: Ye Li <ye.li@nxp.com>
generated by cgit v1.1 at 2024-11-26 16:33:22 +0000