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* powerpc/km82xx: rework DIP switch detectionHuber, Andreas2011-05-10-9/+84
| | | | | | | | | | | | | Introduce a struct for the BFTICU FPGA to increase the readability of the code. And the define CONFIG_SYS_BFTICU_BASE was removed because the CONFIG_SYS_FPGA_BASE is already the base value for BFTICU registers. Signed-off-by: Andreas Huber <andreas.huber@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de>
* powerpc/km82xx: rename mgcoge files to km82xxHolger Brunck2011-05-10-2/+2
| | | | | | | | | | | | | The directory and file mgcoge was renamed to km82xx. Because other keymile 82xx will follow and will use the same platform code. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/km82xx: cleanup coding style for mgcoge.cHolger Brunck2011-05-10-148/+149
| | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* km/common: remove hdlc_enet implementationHolger Brunck2011-05-10-905/+1
| | | | | | | | | | | | | The hdlc implementation for mgcoge was initially developed, but later on not used. Remove the C files, the references in mgcoge.c and the Makefile to decrease maintenance effort. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* cramfs: make cramfs usable without a NOR flashHeiko Schocher2011-05-10-2/+12
| | | | | | | | cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* cramfs: fix bug in using CONFIG_CRAMFS_CMDLINEHeiko Schocher2011-05-10-1/+1
| | | | | | | | | | | | do not define own flash_info variable, instead use the flash_info variable defined in your flash driver. Signed-off-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-05-10-248/+135
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| * MIPS: Move timer code to arch/mips/cpu/$(CPU)/Shinya Kuribayashi2011-05-10-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Introduce --gc-sections for MIPSDaniel Schwierzeck2011-05-10-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | All architectures but MIPS are using --gc-sections on final linking. This patch introduces that feature for MIPS to reduce the memory and flash footprint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Coding style cleanups on common assembly filesShinya Kuribayashi2011-05-07-107/+93
| | | | | | | | | | | | | | | | | | | | Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Remove mips_cache_lock() featureShinya Kuribayashi2011-05-07-100/+0
| | | | | | | | | | | | | | | | | | As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS] Request for the 'mips_cache_lock()' removal), such feature is no longer needed for current MIPS implementation of U-Boot, and no one in the tree uses it for years. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-05-10-3/+1
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| * mpc83xx: restrict UTMI PHY configuration to 831x partsKim Phillips2011-04-04-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.e, to those parts that have PHY_CLK_VALID bits in their USB CONTROL registers: mpc8308 WU_INT, PHY_CLK_SEL, USB_EN, WU_INT_EN, ULPI_INT_EN mpc831x PHY_CLK_VALID, WU_INT, CLKIN_SEL, PHY_CLK_SEL, UTMI_PHY_EN, PLL_RESET, REFSEL, OTG_PORT, KEEP_OTG_ON, LSF_EN, USB_EN, ULPI_INT_EN mpc834x USB_EN, ULPI_INT1_EN (MPH only), ULPI_INT0_EN mpc837x USB_EN, ULPI_INT_EN (mpc832x, mpc8360 don't have a USB_EHCI_FSL compatible controller) this prevents non-831x parts from never completing cpu_init_f(), because the (non-existent) PHY_CLK_VALID bit never gets set. Reported-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Tested-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
* | IDE: fix compiler warningsWolfgang Denk2011-04-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | The changes introduced by commit 0abddf8 ``cmd_ide: enhance new feature "CONFIG_IDE_AHB"'' caused compiler warnings like cmd_ide.c: In function 'ide_init': cmd_ide.c:716: warning: assignment from incompatible pointer type Constify the respective function arguments to fix this. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | common/cmd_mdio.c: fix compile warningAnatolij Gustschin2011-04-30-2/+2
| | | | | | | | | | | | | | | | cmd_mdio.c: In function 'mdio_read_ranges': cmd_mdio.c:97: warning: comparison is always false due to limited range of data type Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com>
* | miiphy: miiphyutil.c: fix compile warningAnatolij Gustschin2011-04-30-4/+8
| | | | | | | | | | | | | | | | | | | | Fix warning introduced while recent PHY Lib changes: miiphyutil.c: In function 'miiphy_read': miiphyutil.c:304: warning: comparison is always false due to limited range of data type Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-30-128/+1252
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| * | fsl-ddr: Fix mixed-case macro namesKyle Moffett2011-04-29-9/+9
| | | | | | | | | | | | | | | Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 64M on FSL 85xx boardsKumar Gala2011-04-29-42/+42
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_BOOTMAPSZ has been 64M on these boards for some time so we should also allow the kernel image to be up to 64M decompressed. This also matches what we pass to the OS based on the ePAPR specification. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI support on P1022DSJiang Yutang2011-04-29-0/+18
| | | | | | | | | | | | | | | Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI support for p1_p2_rdbPriyanka Jain2011-04-29-2/+16
| | | | | | | | | | | | | | | | | | | | | Also added support to save env to spi flash in case of SPIBOOT. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI controller & SPI boot support on P2020DSJerry Huang2011-04-29-0/+29
| | | | | | | | | | | | | | | | | | Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: eSPI and eSPI controller supportMingkai Hu2011-04-29-7/+342
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | tsec: Fix MDIO on devices with eTSEC2Andy Fleming2011-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tsec driver was defining the default MDIO address as the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first TSEC's registers are separated from the MDIO registers. Use the existing MDIO_BASE_ADDR, instead. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala2011-04-28-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi2011-04-28-16/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi2011-04-28-17/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi2011-04-28-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi2011-04-28-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl: add 'pixis_reset dump' commandTimur Tabi2011-04-28-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | Add the 'pixis_reset dump' command, which displays the contents of the PIXIS registers. This command is only available if DEBUG is defined. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/86xx: remove empty board_early_init_f()Timur Tabi2011-04-28-7/+0
| | | | | | | | | | | | | | | | | | | | | Remove an empty board_early_init_f() from the MPC8641HPCN board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock2011-04-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips2011-04-27-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu2011-04-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang2011-04-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala2011-04-27-10/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve2011-04-27-0/+116
| | | | | | | | | | | | | | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve2011-04-27-3/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Fix Wrong PCIe 3 virtual address on corenet_ds platformsTrübenbach, Ralf2011-04-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a wrong address define in corenet_ds.h (used by P4080DS.h, P3041DS.h, P5020DS.h). Since board/Freescale/corenet_ds/tlb.c does not use the CONFIG_SYS_PCIE3_MEM_VIRT define (uses CONFIG_SYS_PCIE1_MEM_VIRT with a fix offset instead) this has no effect to the functionality. But it may be important for changes in the future? Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add device tree fixup for bman portalHaiying Wang2011-04-27-1/+33
| | | | | | | | | | | | | | | | | | | | | Fix fdt bportal to pass the bman revision number to kernel via device tree. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdbRamneek Mehresh2011-04-27-0/+16
| | | | | | | | | | | | | | | | | | Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * | powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoCDipen Dudhat2011-04-27-0/+71
| | | | | | | | | | | | | | | Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Change CS timing params before changing CS properties on IFCDipen Dudhat2011-04-27-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | To make sure that machine change operation work successfully, change timing parameters first before changing machine for chip select on IFC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support to save environment in SD card on p1_p2_rdbPriyanka Jain2011-04-27-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | If we boot from a SD card use it for the environment as well. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | cmd_nvedit.c: clean up with checkpatchMacpaul Lin2011-04-30-75/+73
| | | | | | | | | | | | | | | | | | | | | Code clean up of cmd_nvedit.c by using checkpatch.pl. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Acked-by: Detlev Zundel <dzu@denx.de>
* | | cmd_ide: enhance new feature "CONFIG_IDE_AHB"Macpaul Lin2011-04-30-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although most IDE controller is designed to be connected to PCI bridge, there are still some IDE controller support AHB interface for SoC design. The driver implementation of these IDE-AHB controllers differ from other IDE-PCI controller, some additional registers and commands access is required during CMD/DATA I/O. Hence a configuration "CONFIG_IDE_AHB" in cmd_ide.c is required to be defined to support these kinds of SoC controllers. Such as Faraday's FTIDE020 series and Global Unichip's UINF-0301. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* | | spi: add new driver for OpenCores tiny_spiThomas Chou2011-04-30-0/+249
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for OpenCores tiny_spi. http://opencores.org/project,tiny_spi Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | | zlib: split up to match original source treeMike Frysinger2011-04-30-2219/+2317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While looking to upgrade to zlib-1.2.5, the current mondo merge of multiple files into a single was making things way more difficult than it should have been. Hard to pick out what has been changed to port it to U-Boot, been removed as useless, and bug fixes added after the fact. So split the single file up into the original file names, and merge non-essential changes back from the original tree (for some reason, style in code in a bunch of places was changed to U-Boot style even though this isn't "U-Boot" code). The original build style is retained -- we have a single zlib.c that includes all the other files, and that is the only file we compile. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | tools/env: document current cross-compilation issues and workaroundLuca Ceresoli2011-04-30-0/+6
| | | | | | | | | | | | Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
* | | Handle most LDSCRIPT setting centrallyScott Wood2011-04-30-539/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, some linker scripts are found by common code in config.mk. Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is sometimes in arch config.mk and sometimes in board config.mk. Some are found using an arch-specific rule for looking in CPUDIR, etc. Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds. Replace all of this -- except for a handful of boards that are actually selecting a linker script in a unique way -- with centralized ldscript finding. If board code specifies LDSCRIPT, that will be used. Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used. If neither of these are specified, then the central config.mk will check for the existence of the following, in order: $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds $(TOPDIR)/$(CPUDIR)/u-boot.lds Some boards (sc3, cm5200, munices) provided their own u-boot.lds that were dead code, because they were overridden by a CPUDIR u-boot.lds under the old powerpc rules. These boards' own u-boot.lds have bitrotted and no longer work -- these lds files have been removed. Signed-off-by: Scott Wood <scottwood@freescale.com> Tested-by: Graeme Russ <graeme.russ@gmail.com>
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