summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* USB-CDC: Do not rename netdev after its registrationVitaly Kuzmichev2011-01-19-3/+2
| | | | | | | Calling eth_bind at usb_eth_init time causes renaming of the network device from 'usb_ether' to 'usb0'. Fixing this to keep the first name. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
* usb_ether: register usb ethernet gadget at each eth initLei Wen2011-01-19-4/+8
| | | | | | | | | | | | Since the ether may not be the only one usb gadget would be used in the uboot, it is neccessary to do the register each time the eth begin to work to make usb gadget driver less confussed when we want to use two different usb gadget at the same time. Usb gadget driver could simple ignore the register operation, if it find the driver has been registered already. Signed-off-by: Lei Wen <leiwen@marvell.com>
* Escape minus signs in manpageLoïc Minier2011-01-19-4/+4
| | | | | | | | | | | By default, "-" chars are interpreted as hyphens (U+2010) by groff, not as minus signs (U+002D). Since options to programs use minus signs (U+002D), this means for example in UTF-8 locales that you cannot cut and paste options, nor search for them easily. (Reported by lintian.) Signed-off-by: Loïc Minier <loic.minier@linaro.org>
* Fix typo ("comand" instead of "command")Loïc Minier2011-01-19-1/+1
| | | | Signed-off-by: Loïc Minier <loic.minier@linaro.org>
* cmd_jffs2: Fix get_part_sector_size_nor() overflow bugPeter Tyser2011-01-19-1/+1
| | | | | | | | | | | | | | When a flash partition was positioned at the very top of a 32-bit memory map (eg located at 0xf8000000 with a size of 0x8000000) get_part_sector_size_nor() would incorrectly calculate the partition's ending address to 0x0 due to overflow. When the overflow occurred get_part_sector_size_nor() would falsely return a sector size of 0. A sector size of 0 results in subsequent jffs2 operations failing. To workaround the overflow subtract 1 from calculated address of the partition endpoint. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Replace "FLASH" strings with "Flash" or "flash"Peter Tyser2011-01-19-13/+13
| | | | | | | | There's no compelling reason to have the output on bootup or the "flinfo" command print "flash" in uppercase, so use the proper case where appropriate. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* NET: lan91c96: Correct chip detect logicYanjun Yang2011-01-18-1/+1
| | | | | | | The lan91c96_detect_chip routine is not correct according to the manual. Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>
* lib: add crc7 from LinuxThomas Chou2011-01-18-0/+77
| | | | | | | | | Crc7 is used to compute mmc spi command packet checksum. Copy from linux-2.6 lib/crc7.c include/linux/crc7.h commit ad241528c4919505afccb022acbab3eeb0db4d80 Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* rtc: add support for Micro Crystal RV-3029-C2 RTCHeiko Schocher2011-01-18-0/+125
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc5200, digsy_mtc: add support for rev5 board versionHeiko Schocher2011-01-18-6/+197
| | | | | | | | | | | | | | | | | | | | | | | | | difference to previous board version: - M29W128GH flash from Numonyx - SDRAM ISSI IS45S16800 (Option A2 105°C) - rev5 uses RTC RV-3029-C2 - update cs0 and cs1 baseaddr and length depending on the detected flash size. - added Werner Pfister <Pfister_Werner@intercontrol.de> as maintainer for the digsy board variants - As the M29W128GH needs a special flash_cmd_reset() document that in the new file doc/README.cfi. - move "#endif /* CONFIG_CMD_IDE */" to the right place - remove LOWBOOT config option for digsy_mtc and digsy_mtc_rev5 boards - change doc/README.cfi as Stefan Roese suggested Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> cc: Wolfgang Denk <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Werner Pfister <Pfister_Werner@intercontrol.de> cc: Detlev Zundel <dzu@denx.de>
* ppc, 8xx: remove obsolete km8xx boards from keymileHolger Brunck2011-01-18-1039/+0
| | | | | | | | | | The MPC852 based mgsuvd and kmsupx4 boards from keymile were initially ported but later on not developed further. So the respective files were removed to avoid unneeded merging and maintenance. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher<hs@denx.de>
* Small coding style fix in lib/asm-offsets.cStefan Roese2011-01-17-2/+2
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <monstr@monstr.eu>
* .gitignore: ignore generated u-boot.imxStefano Babic2011-01-17-0/+1
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-17-7586/+2041
|\
| * powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)Kumar Gala2011-01-14-2/+13
| | | | | | | | | | | | | | | | | | Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala2011-01-14-0/+8
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-14-1/+11
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boardsKumar Gala2011-01-14-11/+24
| | | | | | | | | | | | | | CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-18/+25
| | | | | | | | | | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-14-0/+12
| | | | | | | | | | | | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+9
| | | | | | | | | | | | | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-3/+16
| | | | | | | | | | | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add SRIO support to P2020DSLi Yang2011-01-14-1/+23
| | | | | | | | | | | | | | | | The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Convert SBC8641 to use common SRIO init codeKumar Gala2011-01-14-7/+9
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Convert MPC8641HPCN to use common SRIO init codeKumar Gala2011-01-14-21/+14
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Enable common SRIO init codeKumar Gala2011-01-14-3/+15
| | | | | | | | | | | | | | | | Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8569MDS to use common SRIO init codeKumar Gala2011-01-14-6/+9
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8568MDS to use common SRIO init codeKumar Gala2011-01-14-6/+9
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8548CDS to use common SRIO init codeKumar Gala2011-01-14-16/+13
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-56/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * fsl_pci: Update PCIe boot ouputPeter Tyser2011-01-14-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-116/+2
| | | | | | | | | | | | | | Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-45/+13
| | | | | | | | | | | | | | | | | | Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-65/+2
| | | | | | | | | | | | | | | | | | Remove duplicated code in SBC8641 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-65/+19
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-62/+4
| | | | | | | | | | | | | | | | Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-41/+3
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-40/+16
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-37/+13
| | | | | | | | | | | | | | | | Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: wd@denx.de
| * powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-137/+13
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Peter Tyser <ptyser@xes-inc.com>
| * powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-42/+14
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-53/+3
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-102/+17
| | | | | | | | | | | | | | Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-84/+30
| | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-111/+5
| | | | | | | | | | | | | | | | | | Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-89/+13
| | | | | | | | | | | | | | | | | | Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/fsl-pci: Add generic code to setup PCIe controllersKumar Gala2011-01-14-65/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixupKumar Gala2011-01-14-41/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/85xx: Fix bug in dcache_disableKumar Gala2011-01-14-2/+2
| | | | | | | | | | | | | | | | We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-18/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-23 12:31:38 +0000