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* x86: Clean up the FSP support codesBin Meng2014-12-18-290/+279
| | | | | | | | | | | | | | | | | | | | | | | | | This is the follow-on patch to clean up the FSP support codes: - Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(&params) in fsp_init() cannot be removed Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add a README.x86 for U-Boot on x86 supportBin Meng2014-12-18-0/+126
| | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Use 'Link' as the name for the Chromebook Pixel consistently) Change-Id: I158c88653978ff212334f6d4ffeaf49fa81baefe
* x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-11/+11
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SDHCI supportBin Meng2014-12-18-1/+54
| | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-18-0/+7
| | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-1/+42
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Include FSP and CMC binary in the u-boot.rom build rulesBin Meng2014-12-18-2/+10
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-7/+7
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add crownbay defconfig and config.hBin Meng2014-12-18-0/+58
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+112
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-18-0/+1
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-12/+34
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-8/+14
| | | | | | | | | | To avoid having two microcode formats, adjust the build system to support obtaining the microcode from the device tree, even in the case where it must be made available before the device tree can be accessed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+369
| | | | | | | | | | | Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Integrate Tunnel Creek processor microcodeBin Meng2014-12-18-0/+368
| | | | | | | | Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
| | | | | | | | | | | | | There are several problems in the code. The device tree decode is incorrect in ways that are masked due to a matching bug. Both are fixed. Also microcode_read_rev() should be inline and called before the microcode is written. Note: microcode writing does not work correctly on ivybridge for me. Further work is needed to resolve this. But this patch tidies up the existing code so that will be easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-1374/+1504
| | | | | | | | There are new microcode revisions available. Update them. Also change the format so that the first 48 bytes are not omitted from the device tree data. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move microcode updates into a separate directorySimon Glass2014-12-18-2/+2
| | | | | | | We might end up with a few of these, so put them in their own directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Add support for early microcode accessSimon Glass2014-12-18-8/+103
| | | | | | | | | | | | | | | | | | | Some Intel CPUs use an 'FSP' binary blob which provides an inflexible means of starting up the CPU. One result is that microcode updates can only be done before RAM is available and therefore parsing of the device tree is impracticle. Worse, the addess of the microcode update must be stored in ROM since a pointer to its start address and size is passed to the 'FSP' blob. It is not possible to perform any calculations to obtain the address and size. To work around this, ifdtool is enhanced to work out the address and size of the first microcode update it finds in the supplied device tree. It then writes these into the correct place in the ROM. U-Boot can then start up the FSP correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Use a structure for the file/address listSimon Glass2014-12-18-6/+18
| | | | | | | | | Rather than two independent arrays, use a single array of a suitable structure. Also add a 'type' member since we will shortly add additional types. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Display filename when file errors are reportedSimon Glass2014-12-18-12/+18
| | | | | | | | When a file is missing it helps to know which file. Update the error message to print this information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Correct a debug() missing parameterSimon Glass2014-12-18-1/+2
| | | | | | | | This is missing a parameter. Fix it to avoid a warning when debug is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: UniPhier: enable CONFIG_CMD_DMMasahiro Yamada2014-12-18-0/+2
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: select CONFIG_SPLMasahiro Yamada2014-12-18-3/+1
| | | | | | Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: use DRAM area for init stack of normal imageMasahiro Yamada2014-12-18-0/+4
| | | | | | | The normal image is working on DRAM. It is better to use DRAM also for init stack than L2 cache. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada2014-12-18-4/+0
| | | | | | init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada2014-12-18-15/+15
| | | | | | | The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-16-60/+389
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| * mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-29/+36
| | | | | | | | | | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * qe/deep-sleep: modify qe deep-sleep for generic boardZhao Qiang2014-12-15-0/+11
| | | | | | | | | | | | | | | | Deep sleep for generic board is supported now, modify qe deep-sleep code to adapt it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * p5040ds: changed liodn offsetsTudor Laurentiu2014-12-15-12/+12
| | | | | | | | | | | | | | | | | | Offsets were overlaping, causing pamu access violations in hypervised scenarios. Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: Fix RNG instantiation failure.gaurav rana2014-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/T10xx: Fix number of portalsJeffrey Ladouceur2014-12-15-8/+8
| | | | | | | | | | | | | | | | | | | | | | Following boards has incorrect number of portals defined. powerpc/T102xQDS powerpc/T102xRDB powerpc/T1040QDS powerpc/T104xRDB Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+267
| | | | | | | | | | | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: update ft_fixup_port to differentiate dual-role macShengzhou Liu2014-12-15-5/+16
| | | | | | | | | | | | | | | | | | | | we need to differentiate dual-role MACs into two types: MACs with 10GEC enumeration consistent with DTSEC enumeration(defined by CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Fix DDR TLB mapping leftoverYork Sun2014-12-15-4/+8
| | | | | | | | | | | | | | | | | | | | Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de> CC: Scott Wood <scottwood@freescale.com>
| * driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun2014-12-15-1/+20
| | | | | | | | | | | | | | | | | | | | For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/p2041rdb: enable generic board configsShaohui Xie2014-12-15-0/+2
| | | | | | | | | | | | | | | | | | Add following configs in header file: CONFIG_SYS_GENERIC_BOARD CONFIG_DISPLAY_BOARDINFO Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4240rdb: Convert to use generic board codeChunhe Lan2014-12-15-0/+2
| | | | | | | | | | Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/bsc913x: Convert to use generic board codeharninder rai2014-12-15-0/+6
| | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-52/+1901
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| * | arm: socfpga: board: Repair Micrel PHY tuningPavel Machek2014-12-16-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add proper error checking into the PHY tuning patch. Make the PHY tunning only happen in case the KSZ9021 PHY is enabled in config. Call the config callback after the tuning finished. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
| * | socfpga: correctly increment freeze_controller_base addressDinh Nguyen2014-12-06-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | socfpga: add missing struct member fifo_triple_byteDinh Nguyen2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | arm: socfpga: DW_SPI: Remove clock info from config headerStefan Roese2014-12-06-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | spi: designware_spi: Some fixes / changesStefan Roese2014-12-06-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese2014-12-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiersStefan Roese2014-12-06-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add Designware (DW) SPI support to config headerStefan Roese2014-12-06-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
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