| Commit message (Collapse) | Author | Age | Lines |
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fix build error when not configure android partition.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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change boot command and recovery command to booti.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Support booti command which can boot from a boot.img
boot.img is a zImage + ramdisk.img + bootargs + boot addr
which include these info can be used to avoid mis match between
kernel and ramdisk, also can avoid commit to chagne default
bootargs.
For example:
> booti mmc1
command will read the boot.img from 1M offset,
and then parser the bootargs and ramdisk
then do the boot from that zImage.
> booti mmc1 recovery
will going to read the recovery's partition no
and offset and boot from recovery image.
this recovery image also a zImage + ramdisk
bootargs:
if uboot have define a env var 'bootargs', booti command
will use this bootargs as kernel cmdline
if you want use boot.img 's bootargs, just type:
> setenv bootargs
in uboot to clear the bootargs in uboot env.
our default uboot env will be NULL in config file.
also, android use boot.img to support OTA.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Remove build warnings for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix cmd_regul build error.
Signed-off-by: Terry Lv <r65388@freescale.com>
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dd read and change voltage support for mx6.
For help, pls type "help regul"
Detail command info:
regul list - List all regulators' name
regul show all - Display all regulators' voltage
regul show core - Show core voltage in mV
regul show periph - Show peripheral voltage in mV
regul show <regulator name> - Show regulator's voltage in mV
regul set core <voltage value> - Set core voltage in mV
regul set periph <voltage value> - Set periph voltage in mV
regul set <regulator name> <voltage value> - Set regulator's voltage in
mV
Example:
MX6Q ARM2 U-Boot > regul list
Name Voltage
vddpu
vddcore
vddsoc
vdd2p5
vdd1p1
vdd3p0
MX6Q ARM2 U-Boot > regul show all
Name Voltage
vddpu 1100000
vddcore 1100000
vddsoc 1200000
vdd2p5 2400000
vdd1p1 1100000
vdd3p0 3000000
MX6Q ARM2 U-Boot > regul show periph
Name Voltage
periph: 1100000
MX6Q ARM2 U-Boot > regul show core
Name Voltage
core: 1100000
MX6Q ARM2 U-Boot > regul set core 1100000
Set voltage succeed!
Name Voltage
core: 1100000
Signed-off-by: Terry Lv <r65388@freescale.com>
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enable mfg profile.
enable recovery mode.
mx6q_sabresd board's usb otg have HW issue, disable it in
android profile.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add MFG tool support in imx6dl U-boot
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Move partition command from nand to sata in mx6 for nand don't need
these partition command.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix a build error when part.c is built in iram u-boot building.
part.c:94: error: redefinition of 'get_dev'
/home/r65388/uboot-imx-v2009.08/uboot-imx/include/part.h:117: error:
previous definition of 'get_dev' was here
make[1]: *** [part.o] Error 1
make[1]: Leaving directory
`/home/r65388/uboot-imx-v2009.08/uboot-imx/disk'
make: *** [disk/libdisk.a] Error 2
Signed-off-by: Terry Lv <r65388@freescale.com>
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Two issues are fixed:
1. Enlarge malloc size to 10K.
2. Too many configs in sabresd's iram config, remove redundent configs.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add mx6dl iram boot config.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add CONFIG_MXC_FEC macro to fec init code.
Add CONFIG_VIDEO_MX5 to ipu init code.
Change temperature function as static.
For in iram boot, FEC configs is not needed, those FEC init code will
cause build errors.
These changes can reduce image size.
Signed-off-by: Terry Lv <r65388@freescale.com>
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CONFIG_DOS_PARTITION, CONFIG_CMD_FAT, CONFIG_CMD_EXT2 are only for
MMC and SATA, remove from NAND config segment
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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remove arm_freq=800 from default env thus keep 1GHz for kernel
Signed-off-by: Jason Liu <r64343@freescale.com>
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enable i.mx6solo config by default
Signed-off-by: Jason Liu <r64343@freescale.com>
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The 32bit DDR script got from the following link:
http://compass.freescale.net/livelink/livelink/225194568/
MX6DL_init_DDR3_400MHZ_32bit_1.0.inc.txt?func=doc.Fetch&nodeid=225194568
The DDR hw connection on the ARM2 board is 64bit wire, but we can make it use
as 32bit, the side effect is that DDR access size will reduce to the half
Signed-off-by: Jason Liu <r64343@freescale.com>
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The script we get from the following link:
http://compass.freescale.net/livelink/livelink/225193471/MX6DL_init_
DDR3_400MHz_64bit_1.1.inc.txt?func=doc.Fetch&nodeid=225193471
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch add the initial support for i.mx6dl ARM2 board
-SD/MMC basic
-DDR 400Mhz,
-FEC,basic
Due to i.mx6dl shares the same board with i.mx6q on ARM2,
the most common code should be the same as the i.mx6q ARM2
So, no need to create one seperate board file for i.mx6dl.
But We can't simply resue anything from the board file since
the i.mx6dl iomux is changed and thus we have to deal with the
difference between i.mx6q and i.mx6dl for the pad setting part.
Signed-off-by: Jason Liu <r64343@freescale.com>
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integrate DDR script http://compass.freescale.net/livelink/
livelink/225147268/rigel_temp.inc.txt?func=doc.Fetch
&nodeid=225147268
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch add i.mx6dl support for fec driver
i.mx6dl and i.mx6dq shares the same ENET IP.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Checkpatch will throw some warnings in iomux-mx6dl.h file as:
WARNING: line over 80 characters
But for the readable, I intend not to fix these warnings, and
linux/uboot upstream also has so many such kind of cases
Acked-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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For ARM2 and Sabreauto, change TTY0 to TTY3 (which is physical UART4)
For SabreSD, Change TTY3 to TTY0 (which is physical UART1)
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Revert "ENGR00162937 - FEC: Fix FEC cannot load kernel accroding tftp."
That commit only worked on specific networks. It broke BOOTP on other
networks.
This reverts commit 51aa554b0655fb10cb7904071e7bb141042390b2.
Signed-off-by: Alan Tull <r80115@freescale.com>
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Add suport for i.MX 6Quad SABRE Smart Device.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Update the config to delete bootcmd_base from the default env settings for
Sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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The system PMIC registers may not be accessible in u-boot via SPI if
function pmic_reg() is called in the latter part of boot up process in u-boot.
It is because the imx_spi_slave structure is allocated from malloc() in
the spi_setup_slave() function. However, this structure is not completely
initialized, which may result in using a dirty control register value
at CSPI during transfer.
memset() the imx_spi_slave structure after malloc() can resolve this problem
Please refer to CT39243849.
Signed-off-by: Robby Cai <R63905@freescale.com>
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change default console to ttymxc1
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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PCIe is power on by defaultt, we need to power down
it in u-boot, it can save more than 1mW during suspend.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix a typo in default config.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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1. C macro don't eval, so the rd_loadaddr will be (CONFIG_LOADADDR + 0x300000)
rather then number, will cause uboot can't boot, change this to a number which
make default boot env correct.
2. update android mx6q saberlite config to align lastest code status.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Micrel phy KSZ9021 Gb speed cannot work well in i.MX6 sabrelite
board. Advertise phy is not 1000Base-T capable, and enet can
work well at 100Mbps mode in 1000M environment(1G cable & 1G hub).
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add fec support for sabreauto board
Need hardware rework:
1. Add R450 10.0k
2. Remove R1105 1k
3. short Pin 1,2 of u516, will impact CAN1
Signed-off-by: Hake Huang <b20222@freescale.com>
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The root cause is the L1 I-cache need invalidation,
now we don't need this workaround, so remove it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Disable the uboot workaround. It will crash the MFGTOOL.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Align latest boot command with user guide.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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We need to check CPU temperature in uboot, if cpu
is too hot, we will let it waiting there until cpu
temperature drop to save region, then go on boot
up.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix fastboot can't used on mmc1 device on android.
caused by the mmc part number use strtoul but it need the partition number < 0 .
So this caused such error.
Fixed by change strtoul to strtol.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Fix incorrect VDDSOC voltage setting in uboot.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add workaround for POR/wdog reset issue, we need to
do a CORE LDO reset everytime POR/wdog reset, otherwise
kernel will crash or hang when we booting more than 2
cores. Root cause is still under investigation, it is
analog/power related issue, may take long time to
identify the root cause, we need to add workaround to make
function ready first. The flow of workaround is as below:
1. Check CORE LDO reset flag, currently stored in SNVS_LPGPR[0];
2. If it is there, clear it, go on boot up system; If not,
Set the flag, configure wdog to timeout in 0.5 seconds, then
disable CORE LDO and wait for wdog timeout;
This workaround will bring 0.5~1 seconds delay of booting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- When the system is very busy(such as play 1080p streaming in local)
the WIFI & FEC performance were very low.
- Enable the patch in uboot for WIFI and FEC performance:
If WIFI connect to PORT2, enable the config:
CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
CONFIG_WIFI_SDHC_PORT2
If WIFI connect to port3, enable the config:
CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
CONFIG_WIFI_SDHC_PORT3
- The solution of the patch:
I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the
high rate of accessing bus.
II. Increase Master 4 priority for FEC.
Increase Master 2 and AHBMAX priority for WIFI.
- Test result:
i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- "bootp" command sometime cannot work well in i.MX53 platform.
- Cause:
Phy detect cable link need some time, so need wait the complete
of cable detect.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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For uImage's size of mx6q is larger than 3M, we enlarge mmc read size to
4M in default env.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix the ENET PHY settings on MX6 Sabre-lite to enable Master mode
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Fix recovery key detection, the VOL_DN key is low assert.
Or it will always enter recovery mode.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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As we want TF to be default boot media.
Then SD slot can be used by WIFI dongle.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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add android mx6q sabrelite configure file.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add mx6q sabrelite board support for fastboot and recovery.
add recovery key check, same key as in MX53_SMD.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add support for otg in MX6Q uboot to enable fastboot function.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code
Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.
There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily
The MMU Change can be concluded as the following
- Cacheable and Uncacheable SDRAM allocation changes to
Phys Virtual Size Property
---------- ---------- -------- ----------
0x10000000 0x10000000 256M cacheable
0x80000000 0x20000000 16M uncacheable
0x81000000 0x21000000 240M cacheable
- TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
of SDRAM. This address makes sure that the text section of U-boot have the
same Physical and Virtural address, thus the PC don't need to change when
MMU is enabled. Also the text section is all allocated in cacheable memory,
which may increase excecution performance.
- Since this SDRAM allocation avoid overlap in physical memory between
cacheable and uncacheable memory, the implementation of __ioremap can be
ignored
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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