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* sf: Tidy up public and private header filesSimon Glass2014-10-22-60/+73
| | | | | | | | Since spi_flash.h is supposed to be the public API for SPI flash, move private things to sf_internal.h. Also tidy up a few comment nits. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* exynos: universal_c210: Move to driver model soft_spiSimon Glass2014-10-22-62/+14
| | | | | | | Adjust this board to use the driver model soft_spi implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Add documentation on how to convert over SPI driversSimon Glass2014-10-22-0/+594
| | | | | | | | This README is intended to help maintainers move their SPI drivers over to driver model. It works through the required steps with an example. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-336/+190
| | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Add soft_spi implementationSimon Glass2014-10-22-0/+287
| | | | | | | | Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Remove SPI_INIT featureSimon Glass2014-10-22-8/+0
| | | | | | | | | | | | This feature provides for init of a single SPI port for the soft SPI feature. It is not really compatible with driver model since it assumes a single SPI port. Also, inserting SPI init into the driver by means of a #define is not very nice. This feature is not used by any active boards, so let's remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Rename soft_spi.c to soft_spi_legacy.cSimon Glass2014-10-22-1/+1
| | | | | | | | Reserve the 'normal' name for use by driver model, and rename the old driver so that it is clear that it is for 'legacy' drivers only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-128/+76
| | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Adjust cmd_spi to work with driver modelSimon Glass2014-10-22-8/+31
| | | | | | | | | | | Driver model uses a different way to find the SPI bus and slave from the numbered devices given on the command line. Adjust the code to suit. We use a generic SPI device, and attach it to the SPI bus before performing the transaction. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: Add spi.h header to a few filesSimon Glass2014-10-22-0/+3
| | | | | | | | Some files are using SPI functions but not explitly including the SPI header file. Fix this, since driver model needs it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: Remove spi_init() from board_r.c when using driver modelSimon Glass2014-10-22-1/+1
| | | | | | | | | | | Driver model does its own init, so we don't need this. There is still a call in board_f.c but it is only enabled by CONFIG_HARD_SPI. It is easy enough to disable that option when converting boards which use it to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: sandbox: Add a SPI emulation uclassSimon Glass2014-10-22-0/+62
| | | | | | | | | | | | | | | | | U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Add a uclass for SPISimon Glass2014-10-22-4/+650
| | | | | | | | | | | | | | | | Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
* dm: core: Add a clarifying comment on struct udevice's seq memberSimon Glass2014-10-22-2/+5
| | | | | | | The sequence number is unique within the uclass, so state this clearly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: core: Allow parents to pass data to children during probeSimon Glass2014-10-22-1/+25
| | | | | | | | | | | Buses sometimes want to pass data to their children when they are probed. For example, a SPI bus may want to tell the slave device about the chip select it is connected to. Add a new function to permit the parent data to be supplied to the child. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: core: Add functions for iterating through device childrenSimon Glass2014-10-22-1/+78
| | | | | | | | Buses need to iterate through their children in some situations. Add a few functions to make this easy. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sandbox: dts: Add a SPI device and cros_ec deviceSimon Glass2014-10-22-0/+51
| | | | | | | | | | | Add a SPI device which can be used for testing SPI flash features in sandbox. Also add a cros_ec device since with driver model the Chrome OS EC emulation will not otherwise be available. Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Move serial to driver modelSimon Glass2014-10-22-183/+75
| | | | | | | Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Mark exynos5 console as pre-relocSimon Glass2014-10-22-0/+1
| | | | | | We will need the console before relocation, so mark it that way. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: gpio: Convert to driver modelSimon Glass2014-10-22-179/+340
| | | | | | | Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Make sure that GPIOs are requestedSimon Glass2014-10-22-9/+62
| | | | | | | | | | With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Tidy up GPIO definesSimon Glass2014-10-22-10/+11
| | | | | | | | | The defines at the top of the GPIO driver use single-character names for parameters which are not very descriptive. Improve these to use descriptive parameter names. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Tidy up GPIO headersSimon Glass2014-10-22-22/+11
| | | | | | | | | The wrong header is being included, thus requiring the code to re-declare the generic GPIO interface in each GPIO header. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Move s5p_goni to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for s5p_goni. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Move smdkc100 to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for smdkc100. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Add pinctrl settings for s5p_goniSimon Glass2014-10-22-0/+280
| | | | | | | These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Add pinctrl settings for smdkc100Simon Glass2014-10-22-0/+187
| | | | | | | These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: dts: Adjust device tree files for U-BootSimon Glass2014-10-22-0/+159
| | | | | | | | | | The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: dts: Remove unused pinctrl information to save spaceSimon Glass2014-10-22-2098/+0
| | | | | | | | | | We don't include the pinctrl functions for U-Boot as they use up quite a bit of space and are not used. We could instead perhaps eliminate this material with fdtgrep, but so far this tool has not made it to upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Bring in pinctrl dts files from Linux kernelSimon Glass2014-10-22-4/+3831
| | | | | | | | | | Bring in required device tree files for pinctrl from Linux v3.14. These are initially unchanged and have a number of pieces not needed by U-Boot. Note that exynos5420 is renamed to exynos54xx here since we want to support exynos5422 also. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: dts: Convert /include/ to #includeSimon Glass2014-10-22-15/+15
| | | | | | | | We should be consistent about this. The kernel has moved to #include which breaks error reporting to some extent but does allow us to include binding files. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: goni: add i2c_init_board()Robert Baldyga2014-10-22-0/+12
| | | | | | | Add proper initialization of GPIO pins used by software i2c. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: add of_match_ptr() macroMasahiro Yamada2014-10-22-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver model supports two ways for passing device parameters; Device Tree and platform_data (board file). Each driver should generally support both of them because some popular IPs are used on various platforms. Assume the following scenario: - The driver Foo is used on SoC Bar and SoC Baz - The SoC Bar uses Device Tree control (CONFIG_OF_CONTROL=y) - The SoC Baz does not support Device Tree; uses a board file In this situation, the device driver Foo should work with/without the device tree control. The driver should have .of_match and .ofdata_to_platdata members for SoC Bar, while they are meaningless for SoC Baz; therefore those device-tree control code should go inside #ifdef CONFIG_OF_CONTROL. The driver code will be like this: #ifdef CONFIG_OF_CONTROL static const struct udevice_id foo_of_match = { { .compatible = "foo_driver" }, {}, } static int foo_ofdata_to_platdata(struct udevice *dev) { ... } #endif U_BOOT_DRIVER(foo_driver) = { ... .of_match = of_match_ptr(foo_of_match), .ofdata_to_platdata = of_match_ptr(foo_ofdata_to_platdata), ... } This idea has been borrowed from Linux. (In Linux, this macro is defined in include/linux/of.h) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: fix include guardMasahiro Yamada2014-10-22-0/+1
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: include <linker_lists.h> from platdata.h and uclass.hMasahiro Yamada2014-10-22-0/+3
| | | | | | | | | The header files include/dm/platdata.h and include/dm/uclass.h use ll_entry_declare(); therefore they depend on include/linker_lists.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* linker_lists: include <linux/compiler.h>Masahiro Yamada2014-10-22-0/+2
| | | | | | | | The header file include/linker_lists.h uses __aligned(); therefore it depends on include/linux/compiler.h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: simplify the loop in lists_driver_lookup_name()Masahiro Yamada2014-10-22-8/+1
| | | | | | | | | | | | | | | | | | | | if (strncmp(name, entry->name, len)) continue; /* Full match */ if (len == strlen(entry->name)) return entry; is equivalent to: if (!strcmp(name, entry->name)) return entry; The latter is simpler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* dm: do not check the existence of uclass operationMasahiro Yamada2014-10-22-4/+0
| | | | | | | | | | | | | | | | | | The function uclass_add() checks uc_drv->ops as follows: if (uc_drv->ops) { dm_warn("No ops for uclass id %d\n", id); return -EINVAL; } It seems odd because it warns "No ops" when uc_drv->ops has non-NULL pointer. (Looks opposite.) Anyway, most of UCLASS_DRIVER entries have no .ops member. This check makes no sense. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: fix commentsMasahiro Yamada2014-10-22-3/+3
| | | | | | | | | The struct udevice stands for a device, not a driver. The driver_info.name is a driver's name, which is referenced to bind devices. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-10-20-74/+2558
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| * ls102x: Add support for secure boot and enable blob commandRuchika Gupta2014-10-16-0/+16
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+29
| | | | | | | | | | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: Add command for encapsulating/decapsulating blobsRuchika Gupta2014-10-16-2/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure bootRuchika Gupta2014-10-16-1/+9
| | | | | | | | | | | | | | | | | | | | | | By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+39
| | | | | | | | | | | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+91
| | | | | | | | | | | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+1834
| | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-6/+29
| | | | | | | | | | | | | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Move SEC CCSR definition to common includeRuchika Gupta2014-10-16-66/+89
| | | | | | | | | | | | | | | | | | Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/P1010RDB:Update RESET_VECTOR_ADDRESS for 768KB u-boot sizeRuchika Gupta2014-10-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for P1010 SPI Flash Secure boot target. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Modified subject to P1010RDB] Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-12-23 14:21:49 +0000