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* mmc: postponed needless timer initializationMateusz Zalega2014-05-23-1/+4
| | | | | | | | | | mmc_init() doesn't call get_timer() anymore if MMC is already initialized. <panto> Minor formatting fix. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
* Add board_mmc_init(...) function for init mmc1 onlyHannes Petermaier2014-05-23-2/+9
| | | | | | | | | Since B&R boards uses only MMC-Controller #1, it only wastes time if we initialize #0 first to see that there is nothing. Cc: <trini@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driverYe.Li2014-05-22-14/+9
| | | | | | | | | | | | | | | When configure the fsl_esdhc driver to PIO mode by defining "CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail. Two bugs in the driver to cause the issue: 1. The read buffer was invalidated after reading from DATAPORT register, which should be only applied to DMA mode. The valid data in cache was overwritten by physical memory. 2. The watermarks are not set in PIO mode, will cause according state not be set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-05-16-327/+578
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| * powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE bootLiu Gang2014-05-16-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs: remove c=ffe from default environmentKim Phillips2014-05-16-18/+9
| | | | | | | | | | | | | | | | | | | | | | AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Edward Swarthout <ed.swarthout@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPLPrabhakar Kushwaha2014-05-16-268/+450
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NANDAneesh Bansal2014-05-16-1/+1
| | | | | | | | | | | | | | | | | | In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platformramneek mehresh2014-05-16-0/+6
| | | | | | | | | | | | | | | | P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/usb : Define usb control register mask for w1c bitsNikhil Badola2014-05-16-5/+12
| | | | | | | | | | | | | | | | | | | | Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Added B4460 supportShaveta Leekha2014-05-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/85xx: Add T4160RDB board supportChunhe Lan2014-05-16-0/+5
| | | | | | | | | | | | | | | | | | T4160RDB shares the same platform as T4240RDB. T4160 is a low power version of T4240, with the eight e6500 cores, two DDR3 controllers, and same peripheral bus interfaces. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/pci: Add workaround for erratum A-005434Chunhe Lan2014-05-16-2/+11
| | | | | | | | | | | | | | | | | | | | By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t104xrdb: Toggle deep sleep management signals after resumeTang Yuantian2014-05-16-0/+2
| | | | | | | | | | | | | | | | | | T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/freescale: Move CRC32 offset in NXID v1 data formatEbony Zhu2014-05-16-3/+4
| | | | | | | | | | | | | | | | | | | | According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: phy/vitesse: Add support for VSC8664 phy moduleChunhe Lan2014-05-16-0/+46
| | | | | | | | | | | | | | | | This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | patman: Suppress duplicate signoffs only for real patchesSimon Glass2014-05-16-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | There is an unfortunate bug in the signoff suppression logic. The first pass is performed with 'git log', and all signoffs are added to the supression set, such that the second time (when processing the real patches) we always suppress the signoffs. Correct this by only suppressing signoffs in the second pass. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Michal Simek <monstr@monstr.eu> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | sandbox: set sandbox's vendor to nullMasahiro Yamada2014-05-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because sandbox is not a real hardware, setting vendor=sandbox is almost meaningless. This commit sets sandbox's vendor field to '-'. It is a good thing that it decreases one level directory hierarchy. The files board/sandbox/sandbox/* have been moved to board/sandbox/*. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | Revert "sandbox: move source files from board/ to arch/sandbox/"Masahiro Yamada2014-05-16-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 258060905e04fe2eb509756ef3b37e23e220a2d6. Conflicts: boards.cfg Wrong patch 25806090 was applied by accident. Revert it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globalsHans de Goede2014-05-14-19/+4
| | | | | | | | | | | | | | | | | | These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | mvtwsi: Fix clock programmingHans de Goede2014-05-14-5/+2
|/ | | | | | | | | | | | | | | | The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-05-13-70/+2257
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| * boards.cfg: fix a configuration error of ep8248 boardMasahiro Yamada2014-05-13-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "make ep8248_config" fails with an error like this: $ make ep8248_config make: *** [ep8248_config] Error 1 Its cause is that there are two entries for "ep8248". The first is around line 652 of boards.cfg. (as Active) The second appears around line 1230. (as Orphan) This bug was accidentally introduced by commit e7e90901. But it is not the author's fault. He just intended to change IDS8247 board. The commiter added ep8248 entry by mistake when he resolved a conflict. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Kim Phillips <kim.phillips@linaro.org> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com>
| * powerpc/freescale: Convert selected boards to generic board architectureYork Sun2014-05-13-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts the following boards to use generic board: MPC8536DS, MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS, P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ying Zhang <b40530@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Haijun.Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/mpc86xx: Fix boot_flag for calling board_init_f()York Sun2014-05-13-0/+1
| | | | | | | | | | | | | | The argument boot_flag of board_inti_f() hasn't been used for powerpc until recent changing to use generic board. Set it to 0 as a proper value. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Fix boot_flag for calling board_init_f()York Sun2014-05-13-6/+12
| | | | | | | | | | | | | | | | | | baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
| * powerpc/freescale: Change the return value of mac_read_from_eeprom()York Sun2014-05-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | The return value has not been checked by its caller, until recent change of using generic board architecture. The error of this function is not critical enough to hang the system. Printing the warning message is enough to catch user's attention. U-boot should continue to boot to give user a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging in the board_init_r(). Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Ignore FDT pointer for non-QEMU in cpu_init_early_f()York Sun2014-05-13-0/+2
| | | | | | | | | | | | | | | | | | The pointer of device tree comes from r3 for QEMU. This is not the case for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for other functions to detect the non-existence of device tree. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
| * powerpc/mpc8572ds: Increase u-boot size to 768KBYork Sun2014-05-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | U-boot image has grown and exceeded the predefined 512KB. Increasing to 768KB to align with other powerpc boards. Tested on MPC8572DS for 32- and 36-bit targets with NOR flash boot. NAND boot is not covered by this patch. Also update board maintainer for these boards. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
| * qe: disable qe when qe-ucode fails to be uploaded for "deep sleep"Zhao Qiang2014-05-13-1/+8
| | | | | | | | | | | | | | | | when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: Zhao Qiang <B45475@freescale.com>
| * PPC 85xx QEMU: Make a generic board fileAlexander Graf2014-05-13-0/+1
| | | | | | | | | | | | | | This patch enables the E500 QEMU board to use the generic cross-arch board infrastructure. Signed-off-by: Alexander Graf <agraf@suse.de>
| * powerpc/mpc85xx: Update TLB CAMs in relocated modeAlexander Graf2014-05-13-0/+1
| | | | | | | | | | | | | | | | We want to use the TLB mapping helpers in relocated mode as well. These helpers need to have awareness of already occupied TLB entries. We already had them in sync in non-relocated mode, but need to resync them when we move into relocated. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC 85xx QEMU: Don't use HID1Alexander Graf2014-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC 85xx QEMU: Always assume 1 coreAlexander Graf2014-05-13-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
| * kmp204x: enable the errata commandValentin Longchamp2014-05-13-0/+1
| | | | | | | | Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: add workaround for A-004849Valentin Longchamp2014-05-13-6/+37
| | | | | | | | | | | | | | | | | | | | This should prevent the problems that the CCF can deadlock with certain traffic patterns. This also fixes the workaround for A-006559 that was not correctly implemented before. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: update the RCWValentin Longchamp2014-05-13-1/+1
| | | | | | | | | | | | | | | | Fix the IRQ/GPIO settings: all the muxed GPIO/external IRQs that are used as internal interrupts are defined as GPIOs to avoid confusion between the internal/external interrupts. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: complete the reset sequence and PRST configurationValentin Longchamp2014-05-13-19/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the reset support for the following devices that was until then not implemented: - BFTIC4 - QSFPs This also fixes the configuration of the prst behaviour for the other resets: Only the u-boot and kernel relevant subsystems are taken out of reset (pcie, ZL30158, and front eth phy). Most of the prst config move to misc_init_f(), except for the PCIe related ones that are in pci_init_board and the bftic and ZL30158 ones that should be done as soon as possible. Only the behavior of the Hooper reset is changed according to the documentation as the application is not able to not configure the switch when it is not reset. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: update the CONFIG_PRAM and CONFIG_KM_RESERVED_PRAM definesValentin Longchamp2014-05-13-4/+6
| | | | | | | | | | | | | | This prevents u-boot from accessing into the reserved memory areas that we have for /var and the logbooks. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: selftest/factory test pin supportValentin Longchamp2014-05-13-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines the post_hotkeys_pressed() function that is used for: - triggering POST memory regions test - starting the test application through the checktestboot command in a script by setting the active bank to testbank The post_hotkeys_pressed return the state of the SELFTEST pin. The patch moves from the complete POST-memory test that is too long in its SLOW version for our production HW test procedure to the much shorter POST-memory-regions test. Finally, the unused #defines for the not so relevant mtest command are removed. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: handle dip-switch for factory settingsStefan Bigler2014-05-13-0/+30
| | | | | | | | | | | | | | | | | | Add readout of dip-switch to revert to factory settings. If one or more dip-switch are set, launch bank 0 that contains the bootloader to do the required action. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kmp204x: Add support for the unit LEDsStefan Bigler2014-05-13-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | The unit LEDs are managed by the QRIO CPLD. This patch adds support for accessing these LEDs in the QRIO. The LEDs then are set to a correct boot state: - UNIT-LED is red - BOOT-LED is on. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
| * powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-10/+57
| | | | | | | | | | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/t208x: enable errata A006261, A006593, A006379Shengzhou Liu2014-05-13-0/+7
| | | | | | | | | | | | | | Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/fman/memac: use default MDIO_HOLD valueShaohui Xie2014-05-13-6/+2
| | | | | | | | | | | | | | | | Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDBAneesh Bansal2014-05-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdbAneesh Bansal2014-05-13-1/+1
| | | | | | | | | | | | | | | | T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
| * powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-1/+1453
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
| * board/b4qds: VID supportShaveta Leekha2014-05-13-0/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
| * board/freescale/common: ZM7300 driverShaveta Leekha2014-05-13-0/+258
| | | | | | | | | | | | | | | | | | | | | | Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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