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* tegra: fdt: Add keyboard definitions for SeaboardAnton Staff2012-05-15-0/+27
| | | | | | | | Seaboard uses a QUERTY keyboard. We add key codes for this to enable key scanning to work. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add keyboard controller definitionAnton Staff2012-05-15-0/+4
| | | | | | | | The Tegra keyboard controller provides a simple interface to a matrix keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add keyboard support to funcmuxSimon Glass2012-05-15-0/+16
| | | | | | | Add funcmux support for the default keyboard mapping. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* input: Add support for keyboard matrix decoding from an fdtBernie Thompson2012-05-15-0/+309
| | | | | | | | | | | | | Matrix keyboards require a key map to be set up, and must also deal with key ghosting. Create a keyboard matrix management implementation which can be leveraged by various keyboard drivers. This includes code to read the keymap from the FDT and perform debouncing. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* input: Add generic keyboard input handlerSimon Glass2012-05-15-0/+578
| | | | | | | | | | | | | Add a module which understands converting key codes (or scan codes) to ASCII characters. It includes FIFO support and can call back to drivers to read new characters when its FIFO is empty. Keycode maps are provided for un-modified, shift and ctrl keys. The plan is to use this module where such mapping is required. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* input: Add linux/input.h for key code supportSimon Glass2012-05-15-0/+155
| | | | | | | | We want to able to decode Linux fdt keymaps, so bring part of this enormous header file over to U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add fdtdec functions to read byte arrayAnton Staff2012-05-15-0/+56
| | | | | | | | | Sometimes we don't need a full cell for each value. This provides a simple function to read a byte array, both with and without copying it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Enable LP0 on SeaboardSimon Glass2012-05-15-0/+25
| | | | | | | This enables LP0 to support suspend / resume on Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add EMC data for Tegra2 SeaboardSimon Glass2012-05-15-0/+37
| | | | | | | | | | | | This adds timings for T20 and T25 Seaboards, using the bindings found here: http://patchwork.ozlabs.org/patch/132928/ We supply both full speed options for normal running, and half speed options for testing / development. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: i2c: Add function to find DVC busSimon Glass2012-05-15-0/+21
| | | | | | | | Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus. This allows us to talk to the PMU. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: tegra: Add EMC node to device treeSimon Glass2012-05-15-0/+7
| | | | | | | | | | Add a definition of the memory controller node according to the bindings here: http://patchwork.ozlabs.org/patch/132928/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add EMC settings for SeaboardJimmy Zhang2012-05-15-2/+95
| | | | | | | | | Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Turn off power detect in board initWei Ni2012-05-15-0/+18
| | | | | | | | | | | Tegra core power rail has leakage voltage around 0.2V while system in suspend mode. The source of the leakage should be coming from PMC power detect logic for IO rails power detection. That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' to PWR_DET (APBDEV_PMC_PWR_DET_0). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Set up warmboot code on Nvidia boardsSimon Glass2012-05-15-0/+6
| | | | | | | Call the function to put warmboot boot in a suitable place for resume. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Setup PMC scratch info from ap20 setupYen Lin2012-05-15-0/+6
| | | | | | | | Save SDRAM parameters into the warmboot scratch registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add warmboot implementationYen Lin2012-05-15-0/+869
| | | | | | | | | Add code to set up the warm boot area in the Tegra CPU ready for a resume after suspend. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Set up PMU for Nvidia boardsSimon Glass2012-05-15-0/+6
| | | | | | | Adjust PMU to permit maximum frequency operation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add PMU to manage power suppliesJimmy Zhang2012-05-15-0/+101
| | | | | | | | | | | Power supplies must be adjusted in line with clock frequency. This code provides a simple routine to set the voltage to allow operation at maximum frequency. - Split PMU code into separate TPS6586X driver Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add EMC support for optimal memory timingsJimmy Zhang2012-05-15-0/+404
| | | | | | | | Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add header file for APB_MISC registerSimon Glass2012-05-15-0/+36
| | | | | | | Add a basic header file for this register, to be filled in as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add tegra_get_chip_type() to detect SKUSimon Glass2012-05-15-0/+76
| | | | | | | | | | We want to know which type of chip we are running on - the Tegra family has several SKUs. This can be determined by reading a fuse register, so add this function to ap20. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add flow, gp_padctl, fuse, sdram headersYen Lin2012-05-15-0/+288
| | | | | | | | | | | | | These headers provide access to additional Tegra features. flow - start/stop CPUs sdram - parameters for SDRAM fuse - access to on-chip fuses / security settings gp_padctl - pad control and general purpose registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add crypto library for warmboot codeYen Lin2012-05-15-0/+266
| | | | | | | | Provides an interface to aes.c for the warmboot code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add functions to access low-level Osc/PLL detailsSimon Glass2012-05-15-0/+57
| | | | | | | | Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass() to find out if the Oscillator is bypassed. These are needed by warmboot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move ap20.h header into arch locationSimon Glass2012-05-15-3/+3
| | | | | | | | We want to include this from board code, so move the header into an easily-accessible location. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Add AES crypto libraryYen Lin2012-05-15-0/+669
| | | | | | | | | | Add support for AES using an implementation from Karl Malbrain. This offers small code size (around 5KB on ARM) and supports 128-bit AES only. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* i2c: Add TPS6586X driverSimon Glass2012-05-15-0/+349
| | | | | | | | | This power management chip supports battery charging and a large number of power supplies. This initial driver only provides the ability to adjust the two synchronous buck converters SM0 and SM1 in a stepwise manner. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Add abs() macro to return absolute valueSimon Glass2012-05-15-7/+25
| | | | | | | | | This macro is generally useful to make it available in common. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* fdt: Add function to return next compatible subnodeSimon Glass2012-05-15-0/+32
| | | | | | | | We need to iterate through subnodes of a parent, looking only at compatible nodes. Add a utility function to do this for us. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add function to locate an array in the device treeSimon Glass2012-05-15-0/+30
| | | | | | | | | | fdtdec_locate_array() locates an integer array but does not copy it. This saves the caller having to allocated wasted space. Access to array elements should be through the fdt32_to_cpu() macro. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* i.MX28: Avoid redefining serial_put[cs]()Marek Vasut2012-05-15-0/+2
| | | | | | | | | | | | Do not define serial_putc() and serial_puts() calls if CONFIG_SPL_SERIAL_SUPPORT is set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX28: Check if WP detection is implemented at allMarek Vasut2012-05-15-1/+2
| | | | | | | | | | | If the WP function is NULL, simply assume the card is always RW. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX28: Add battery boot components to SPLMarek Vasut2012-05-15-8/+92
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Reorder battery status functions in SPLMarek Vasut2012-05-15-64/+56
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add LRADC init to i.MX28 SPLMarek Vasut2012-05-15-1/+100
| | | | | | | | | | This code is part of battery boot support for i.MX28. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add LRADC register definitionsMarek Vasut2012-05-15-0/+401
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Shut down the LCD controller before resetMarek Vasut2012-05-15-1/+8
| | | | | | | | | | | | If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add LCDIF register definitionsMarek Vasut2012-05-15-0/+213
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Implement boot pads sampling and reportingMarek Vasut2012-05-15-0/+80
| | | | | | | | | | | This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Improve passing of data from SPL to U-BootMarek Vasut2012-05-15-18/+20
| | | | | | | | | | | | Pass memory size from SPL via structure located in SRAM instead of SCRATCH registers. This allows passing more data about boot from SPL to U-Boot, like the boot mode pads configuration. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* M28EVK: Add SD update commandMarek Vasut2012-05-15-0/+9
| | | | | | | | | | | Add "update_sd_firmware" command to easily reload the SD card of m28evk kit. This comes handy when the board boots from SD card. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* M28EVK: Implement support for new board V2.0Marek Vasut2012-05-15-3/+25
| | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* FEC: Abstract out register setupMarek Vasut2012-05-15-46/+38
| | | | | | | | | | | Abstract out common register setup. This also configured r_cntrl to correct value at registration time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchangedStefano Babic2012-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by: David Jander <david.jander@protonic.nl> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Jander <david.jander@protonic.nl> Acked-by: David Jander <david.jander@protonic.nl> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* i.MX28: Add delay after CPU bypass is clearedMarek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* spi: mxs: Allow other chip selects to workFabio Estevam2012-05-15-0/+10
| | | | | | | | | | | | MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2. Currently only SS0 is supported in the mxs_spi driver. Allow all the three chip select to work by selecting the desired one in bits 20 and 21 of the HW_SSP_CTRL0 register. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* spi: mxs: Introduce spi_cs_is_valid()Fabio Estevam2012-05-15-2/+11
| | | | | | | | Introduce spi_cs_is_valid() for validating spi bus and chip select numbers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mx53loco: Remove unneeded gpio_set_value()Fabio Estevam2012-05-15-3/+2
| | | | | | | | | | There is no need to set the VBUS power enable to 0 first and then to 1. Set it to 1 in the gpio_direction_output() function. While at it, use the standard naming convention for the GPIO comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx53loco: Add CONFIG_REVISION_TAGFabio Estevam2012-05-15-0/+18
| | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx53loco: Turn on VUSB regulatorFabio Estevam2012-05-15-0/+10
| | | | | | | | | | | | | | | | | | On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator so that the mx53 USBH1 PHY receives the 3.3V voltage. Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the commands: usb start usb info ,which correctly detected and printed the USB pen drive information. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
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