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* powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-19/+28
| | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-128/+129
| | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Update README.srio-boot-corenetLiu Gang2012-08-23-37/+33
| | | | | | | | | | | | | | | Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditionalYork Sun2012-08-23-3/+56
| | | | | | | | | | | | | | | | | This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()Scott Wood2012-08-22-22/+25
| | | | | | | | | This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used before the final write to LSOR that initiates the transaction, to ensure all the other set up has been completed. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: Stack Pointer not properly alignedJoakim Tjernlund2012-08-22-3/+2
| | | | | | | | | The code first aligns the SP to 16 then subtract 8, making it 8 bytes aligned. Furthermore the initial stack frame not quite correct either. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc85xx: Initial SP alignment is wrong.Joakim Tjernlund2012-08-22-11/+5
| | | | | | | | | | | | PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Makefile: fix HAVE_VENDOR_COMMON_LIBScott Wood2012-08-17-2/+2
| | | | | | | | | | | Commit 8b5a02640adf77301f943e8754992c50df004e8a ("Makefile: cosmetic: optimize usage of LIBS-y") broke the build of boards that have a board vendor "common" directory, by introducing a space between "LIBS-" and "y". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* mtd/cfi_flash: fix write problems for Numonyx P33/30 32 MBit flashsHolger Brunck2012-08-13-22/+44
| | | | | | | | | | | | | | | | | | commit 54652991 Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads to problems for smaller versions of this chip e.g. the 32Mbit version with deviceid 0x16 on mgcoge. So move the code for this work around to an own function and check previously manufacturer id and device id to not break other flashes which don't need this work around. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Heiko Schocher <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Philippe De Muyter <phdm@macqel.be> cc: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: add support for Spansion flash PPB sector protectionAnatolij Gustschin2012-08-13-0/+59
| | | | | | | | | | Erasing flash sectors protected with persistent protection bit (PPB) mechanism on Spansion flash chips doesn't work. Add sector protection status checking and sector lock and unlock commands to fix this. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* dts/Makefile: Turn off some predefined macrosHorst Kronstorfer2012-08-10-1/+2
| | | | | | | | | | | Add '-ansi' to DTS_CPPFLAGS to avoid unwanted expansion of dts content that matches some predefined macros. Example: A number of PowerPC related *.dts files in the kernel define a property named 'linux,network-index' which (w/o '-ansi') is expanded to '1,network-index' by the preprocessor because of '#define linux 1.' Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
* Add support for DS1388.Kenth Eriksson2012-08-10-0/+27
| | | | | | | | | | Support for DS1388 is added by extending the DS1337 driver. DS1388 is similar to DS1337. The time registers are offset by 1 (due to support for hundreds of seconds), and there is no century bit. The configuration and trickle charge registers are also different. Tested on hardware with Freescale P2010 and DS1388. Signed-off-by: Kenth Eriksson <kenth.eriksson@transmode.com>
* dts/Makefile: Check for empty $(LDSCRIPT)Horst Kronstorfer2012-08-10-2/+3
| | | | | | | | Make sure that $(LDSCRIPT) is not empty before calling process_lds with 'cat $(LDSCRIPT)' else cat will block waiting for input from stdin. Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
* Makefile: cosmetic: optimize usage of LIBS-yDaniel Schwierzeck2012-08-10-13/+7
| | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Makefile: replace LIBS by LIBS-yDaniel Schwierzeck2012-08-10-68/+68
| | | | | | | Synchronize with ALL-y handling and code in spl/Makefile. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Makefile: allow appending to LIB in sub-makefilesDaniel Schwierzeck2012-08-10-1/+1
| | | | | | | | | | | | | | | | | | | | The top Makefile and the SPL Makefile have lines like those: ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS += $(CPUDIR)/omap-common/libomap-common.o endif ifeq ($(SOC),mx5) LIBS += $(CPUDIR)/imx-common/libimx-common.o endif This should be done in the arch/CPU/SoC specific sub-makefiles to keep the top Makefiles clean. This patch also allows adding of new arch/CPU/SoC specific libraries in the future without touching the top Makefiles. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* nds32: fix unused pmu_init warningMike Frysinger2012-08-11-0/+2
| | | | | | | | | | | Fixes the build-time warning: board.c: At top level: board.c:106: warning: 'pmu_init' defined but not used This makes the ifdef logic at the call site match the logic at the function definition. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* nds32: delete unused local variableMike Frysinger2012-08-11-1/+0
| | | | | | | | Fixes the build-time warning: board.c: In function 'board_init_r': board.c:304: warning: unused variable 's' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* nds32: drop bi_enetaddr from global dataMike Frysinger2012-08-11-1/+0
| | | | | | | Nothing is using this, so punt it from the gd. Seems to just be a copy & paste wart from the initial port. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* zfs: Add ZFS filesystem supportJorgen Lundman2012-08-09-1/+4750
| | | | | | | | | | | | | | | | | | | | | U-Boot port is based on sources forked from GRUB-0.97 by Sun in 2004, which can be found here: http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/grub/grub-0.97/stage2/zfs-include/zfs.h Released by Sun for GRUB under the license: * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. GRUB official releases include ZFS in version: ftp://alpha.gnu.org/gnu/grub/grub-1.99~rc1.tar.gz And patched against GRUB Bazaar repository for ashift fixes (4KB HDDs) more conveniently found at github: https://github.com/pendor/grub-zfs/commit/e7b6ef3ac3b9685ac4c394c897b1d4221b7381f1 Signed-off-by: Jorgen Lundman <lundman@lundman.net>
* u-boot: Update yaffs2 file systemCharles Manning2012-08-09-10044/+13517
| | | | | | | | This patch updates the yaffs2 in u-boot to correspond to git://www.aleph1.co.uk/yaffs2 commit id 9ee5d0643e559568dbe62215f76e0a7bd5a63d93 Signed-off-by: Charles Manning <cdhmanning@gmail.com>
* openrisc: Work around potential relocation issuesJulius Baxter2012-08-09-6/+13
| | | | | | | | | | When reset code is in flash, the jump instructions emitted by the compiler are relative instead of absolute jumps. A fix to the reset code to make correct jumps to the beginning of code relocated to RAM have also been added. Signed-off-by: Julius Baxter <juliusbaxter@gmail.com>
* rename EB+MCF-EV123 to its current marketing name EB+CPU5282Jens Scharsig2012-08-09-7/+11
| | | | | | | | | * rename board directory to eb_cpu5282 * rename EB+MCF-EV123_.*config to eb_cpu5282_.*config * add Maintainer for EB+CPU5282 board * rename prompt Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
* Consider CONFIG_ZERO_BOOTDELAY_CHECK when CONFIG_AUTOBOOT_KEYED is setDirk Eibach2012-08-09-0/+5
| | | | | | | | When CONFIG_ZERO_BOOTDELAY_CHECK is not defined, bootdelay==0 prevents the check for console input (as stated in README.autoboot). This must also work in CONFIG_AUTOBOOT_KEYED mode. Signed-off-by: Dirk Eibach <eibach@gdsys.de>
* mkconfig: add support for SPL CPUAllen Martin2012-08-09-1/+31
| | | | | | | | | | | | | Add support for specifying a differnt CPU for main u-boot and SPL u-boot builds. This is done by adding an optional SPL CPU after the main CPU in boards.cfg as follows: normal_cpu:spl_cpu This this case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build. Signed-off-by: Allen Martin <amartin@nvidia.com>
* configs: Remove unused symbol CONFIG_DISCOVER_PHYFabio Estevam2012-08-09-10/+0
| | | | | | CONFIG_DISCOVER_PHY is not used anywhere, so remove it from config files. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Build: Ignore build tree and IDE control fileTimo Ketola2012-08-09-0/+4
| | | | Signed-off-by: Timo Ketola <timo@exertus.fi>
* powerpc: Fix declaration type for I/O functionsPrabhakar Kushwaha2012-08-09-10/+10
| | | | | | | | | Prototype declaration of I/O operation functions are not correct. as both 'extern' and function definition are at same place. Chage protoype declaration as static. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc:Fix return type & parameter passed for I/O functionsPrabhakar Kushwaha2012-08-09-15/+15
| | | | | | | | | | | | Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type u8/u16/u32. Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type uniform across the file changed to u32 Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32 should not be 'int'.Change it to type u8/u16/u32. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* UBIFS: Improve error message when reading superblock failedBernhard Walle2012-08-09-1/+1
| | | | | | | | | | | | | | In addition to the error message also display the error code. I had the problem that my malloc memory was not enough (ENOMEM), and if u-boot had displayed the error code immediately that would have saved me some debugging. Signed-off-by: Bernhard Walle <walle@corscience.de> Use ubifs_err instead of printf. Add "errno=%d" in output as suggested by Albert Aribaud. Signed-off-by: Thomas Weber <weber@corscience.de>
* sandbox: Add basic test for command executionSimon Glass2012-08-09-0/+131
| | | | | | | | | | | | | | | | | | | Since run_command() and run_command_list() are important and a little confusing, add some basic tests to check that the behaviour is correct. Note: I am not sure that this should be committed, nor where it should go in the source tree. Comments welcome. To run the unit tests use the ut_cmd command available in sandbox: make sandbox_config make ./u-boot -c ut_cmd (To test both hush and built-in parsers, you need to manually change CONFIG_SYS_HUSH_PARSER in include/configs/sandbox.h and build/run again) Signed-off-by: Simon Glass <sjg@chromium.org>
* Allow newlines within command environment varsSimon Glass2012-08-09-3/+3
| | | | | | | | | | | | Any environment variable can hold commands to be executed by the 'run' command. The environment variables preboot, bootcmd and menucmd have special code for triggering execution in certain circumstances. We adjust these calls to use run_command_list() instead of run_command(). This change permits these variables to have embedded newlines so that they work the same as the 'source' command. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add run_command_list() to run a list of commandsSimon Glass2012-08-09-65/+102
| | | | | | | | | This new function runs a list of commands separated by semicolon or newline. We move this out of cmd_source so that it can be used by other code. The PXE code also uses the new function. Suggested-by: Michael Walle <michael@walle.cc> Signed-off-by: Simon Glass <sjg@chromium.org>
* Malloc: Fix -Wundef warningsMarek Vasut2012-08-09-3/+3
| | | | | | | | | | In file included from arch/arm/lib/board.c:43:0: include/malloc.h:490:5: warning: "HAVE_MMAP" is not defined [-Wundef] include/malloc.h:590:5: warning: "HAVE_USR_INCLUDE_MALLOC_H" is not defined [-Wundef] include/malloc.h:757:5: warning: "HAVE_MMAP" is not defined [-Wundef] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
* global_data: unify global flag definesMike Frysinger2012-08-09-181/+42
| | | | | | | All the global flag defines are the same across all arches. So unify them in one place, and add a simple way for arches to extend for their needs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* MAKEALL: Allow empty ERR directoryAndy Fleming2012-08-09-2/+2
| | | | | | | | | | | If we build everything correctly with multiple builds, and an ERR directory had been previously created, we failed to report that everything was fine because grep failed to find anything in the ERR directory. Use grep -r, which doesn't complain if there are no input files. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-08-09-62/+285
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs powerpc/mpc85xx: Ignore E bit for BSC9130/1 powerpc/sgmii: To support PHY link state auto detect in SGMII mode powerpc/85xx: improve definition of BR_PHYS_ADDR macro powerpc/p2041: configure the CPLD lane_mux according to RCW powerpc/ddr: fix fsl_ddr_get_dimm_params compile error powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB powerpc/p1022ds: fix DIU/LBC switching with NAND enabled powerpc/p1022ds: add support for SPI and SD boot Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNsTimur Tabi2012-08-08-14/+14
| | | | | | | | | | | | | | | | | | | | The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows which PCI device tree node to look for. The calls to these macros are using a hard-coded string, but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we should use that. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Ignore E bit for BSC9130/1York Sun2012-08-08-2/+0
| | | | | | | | | | | | | | | | Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply timing. Remove them now. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/sgmii: To support PHY link state auto detect in SGMII modeHongtao Jia2012-08-08-8/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PHYs on SGMII riser card are used in SGMII mode with different external IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type under ethernet node should be updated. Otherwise the PHY interrupt can not be handled therefor PHY link state change can not be auto detected. For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed but it's still be kept to guarantee the sgmii mode could work with old device tree. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: improve definition of BR_PHYS_ADDR macroTimur Tabi2012-08-08-23/+21
| | | | | | | | | | | | | | | | The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/p2041: configure the CPLD lane_mux according to RCWShaohui Xie2012-08-08-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/ddr: fix fsl_ddr_get_dimm_params compile errorShaohui Xie2012-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | fsl_ddr_get_dimm_params() should be wrapped by CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of using SPD, it will cause compile error. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is definedShaohui Xie2012-08-08-1/+6
| | | | | | | | | | | | | | | | | | | | ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined and non-NOR u-boot is building, it will cause compile error. Also, add CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash write performance. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GBYork Sun2012-08-08-2/+11
| | | | | | | | | | | | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Early commit eb672e92 works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/p1022ds: fix DIU/LBC switching with NAND enabledTimur Tabi2012-08-08-8/+74
| | | | | | | | | | | | | | | | | | | | | | In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/p1022ds: add support for SPI and SD bootMatthew McClintock2012-08-08-3/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | sh: Add support pin function control using GPIONobuhiro Iwamatsu2012-08-08-0/+822
| | | | | | | | | | | | | | | | Renesas SH and R-Mobile set up device using PFC. This provide the framework. Most codes were brought from linux kernel. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | serial: sh: Add support Renesas R8A7740Hideyuki Sano2012-08-08-7/+14
| | | | | | | | | | | | | | The serial device of R8A7740 has the same structure as SH7372 of SH, etc. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | serial: sh: Add support Renesas SH73A0Nobuhiro Iwamatsu2012-08-08-7/+14
| | | | | | | | | | | | | | The serial device of SH73A0 has the same structure as SH7372 of SH, etc. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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