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* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-109/+247
|\ | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARM: tegra: colibri_t20: fix nand pinmuxMarcel Ziswiler2015-03-30-0/+6
| | | | | | | | | | | | | | | | | | Pingroup ATC seems to come out of reset with config set to NAND, so we need to explicitly configure some other function to this group in order to avoid clashing settings. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BITLucas Stach2015-03-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: update colibri_t20 configurationMarcel Ziswiler2015-03-30-4/+27
| | | | | | | | | | | | | | Bring the Colibri T20 configuration in-line with Apalis/Colibri T30. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix colibri_t20 asix resetMarcel Ziswiler2015-03-30-1/+8
| | | | | | | | | | | | | | | | Fix ASIX USB to Ethernet chip reset. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix colibri_t20 machine typeMarcel Ziswiler2015-03-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: rename colibri_t20 board/configuration/device-treeMarcel Ziswiler2015-03-30-22/+23
| | | | | | | | | | | | | | | | | | | | | | In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: get rid of colibri_t20-commonMarcel Ziswiler2015-03-30-57/+31
| | | | | | | | | | | | | | | | | | | | | | As a preparatory step to renaming the board folder as well first get rid of the colibri_t20-common after having integrated it into colibri_t20_iris for now. While at it also migrate to using NVIDIA's common.mk magic. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: seaboard: Correct the gpio_request() callSimon Glass2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | Requesting a GPIO without a name is not supposed anymore. This causes the request to fail. Add a name so that the serial console works on seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIOSimon Glass2015-03-30-3/+0
| | | | | | | | | | | | | | | | | | This CONFIG is not used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: enable MIPI PAD CTRL support for Tegra124Stephen Warren2015-03-30-0/+26
| | | | | | | | | | | | | | This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinctrl: add support for MIPI PAD control groupsStephen Warren2015-03-30-0/+73
| | | | | | | | | | | | | | | | Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinctrl: minor cleanupStephen Warren2015-03-30-11/+11
| | | | | | | | | | | | | | | | | | | | | | Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinctrl: move Tegra210 code to the correct dirStephen Warren2015-03-30-0/+0
| | | | | | | | | | | | | | | | | | | | | | Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARMv8: enable DM in vexpress64 boardDavid Feng2015-03-27-1/+25
| | | | | | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
| * ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-6/+11
| | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | Prepare v2015.04-rc5Tom Rini2015-03-31-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-456/+673
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| * | ARM: at91: sama5: move the common part of configurations to at91-sama5_common.hWu, Josh2015-04-01-298/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a new configuration file: at91-sama5_common.h. Which includes the configurations that reused by all SAMA5 chips. at91-sama5_common.h includes: - hw macros (clock, text_base and etc.) - default commands. - BOOTARGS - U-Boot common configs. NOTE: NOR flash definition should be put before including the common header. For sama5d3-xplained: - add CMD_SETEXPR For sama5d3xek: - add CMD_SETEXPR - change CONFIG_SYS_MALLOC_LEN to (4*1024*1024) Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * | ARM: atmel: at91sam9n12ek: enable spl supportBo Shen2015-04-01-5/+138
| | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9n12ek boards, now it supports boot up from NAND flash, serial flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: at91sam9x5ek: enable spl supportBo Shen2015-04-01-4/+157
| | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: at91sam9m10g45ek: enable spl supportBo Shen2015-04-01-1/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: arm926ejs: fix clock configurationBo Shen2015-04-01-26/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed. Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Heiko Schocher <hs@denx.de>
| * | ARM: at91: at91sam9n12ek: save the environment to a fat file in MMC cardWu, Josh2015-04-01-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Insteading in mmc's raw sectors, this patch will save the environment in a fat file (uboot.env) in mmc card's first FAT patition by default. If you want to save in mmc's raw sectors, you only need to define CONFIG_ENV_IS_IN_MMC. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: at91: atmel_nand: Support flash based BBTDavid Dueck2015-04-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on-flash bad block table. This makes U-Boot handle an existing BBT correctly. Signed-off-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Andreas Bießmann <andreas.devel@googlemail.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: Josh Wu <josh.wu@atmel.com>
| * | arm, at91: corvus: move MACH_TYPE to defconfigHeiko Schocher2015-04-01-4/+1
| | | | | | | | | | | | | | | | | | move MACH_TYPE into defconfig Signed-off-by: Heiko Schocher <hs@denx.de>
| * | spl_atmel.c: Switch s_init to board_init_fTom Rini2015-04-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an empty stub of s_init(). It can be removed when lowlevel_init becomes s_init. Cc: Bo Shen <voice.shen@atmel.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini@ti.com> [rebased on current master, leave s_init() as empty stub] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: armv7: switch to use common timer functionsBo Shen2015-04-01-61/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8dfafdd (Introduce common timer functions), add common timer functions, we can use them directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: arm9: switch to use common timer functionsBo Shen2015-04-01-59/+18
| | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: sama5d4: display the U-Boot version on LCDWu, Josh2015-04-01-0/+4
| | | | | | | | | | | | | | | | | | | | | This patch will display the U-Boot version on LCD. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* | | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-03-31-462/+133
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| * | | mtd: vf610_nfc: specify transfer size before each transferStefan Agner2015-03-30-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing showed, that commands like STATUS made the buffer dirty when executed with NFC_SECSZ set to the page size. It looks like the controller transfers bogus data when this register is configured. When setting it to 0, the buffer does not get altered while the status command still seems to work flawless. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | mtd: vf610_nfc: mark page as dirty on block eraseStefan Agner2015-03-30-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver tries to re-use the page buffer by storing the page number of the current page in the buffer. The page is only read if the requested page number is not currently in the buffer. When a block is erased, the page number is marked as invalid if the erased page equals the one currently in the cache. However, since a erase block consists of multiple pages, also other page numbers could be affected. The commands to reproduce this issue (on a written page): > nand dump 0x800 > nand erase 0x0 0x20000 > nand dump 0x800 The second nand dump command returns the data from the buffer, while in fact the page is erased (0xff). Avoid the hassle to calculate whether the page is affected or not, but set the page buffer unconditionally to invalid instead. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | nand: yaffs: Remove the "nand write.yaffs" commandPeter Tyser2015-03-30-87/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command is only enabled by one board, complicates the NAND code, and doesn't appear to have been functioning properly for several years. If there are no bad blocks in the NAND region being written nand_write_skip_bad() will take the shortcut of calling nand_write() which bypasses the special yaffs handling. This causes invalid YAFFS data to be written. See http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for an example and a potential workaround. U-Boot still retains the ability to mount and access YAFFS partitions via CONFIG_YAFFS2. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | | nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser2015-03-30-328/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dfu: nand: Verify writesPeter Tyser2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously NAND writes were not verified and could fail silently. Add a verification step after all writes to NAND. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | cmd_nand: Verify writes to NANDPeter Tyser2015-03-30-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously NAND writes were only verified when CONFIG_MTD_NAND_VERIFY_WRITE was defined. On boards without this define writes could fail silently. Boards with CONFIG_MTD_NAND_VERIFY_WRITE could prematurely report failures which ECC could correct. Add a verification step after all "nand write[.x]" commands to ensure the writes were successful. The verification uses ECC for for "normal" writes, but does not for raw and yaffs writes. Some test cases which inject fake bad bits on a 2K page flash are below. Test cases with CONFIG_MTD_NAND_VERIFY_WRITE defined: Example of an ECC write which previously failed when CONFIG_MTD_NAND_VERIFY_WRITE was defined, but now succeeds because ECC is used during verification: nand erase 0 0x10000 dhcp /somefile mw.b 0x10000 0xff 0x2000 mw.b 0x10020 0xfe 1 nand write.raw 0x10000 0x800 1 mw.b 0x1000020 0x01 1 nand write 0x1000000 0x800 0x1800 Test cases without CONFIG_MTD_NAND_VERIFY_WRITE defined: Example of an ECC write which previously silently failed: nand erase 0 0x10000 dhcp /somefile mw.b 0x10000 0xff 0x2000 mw.b 0x10020 0x00 1 nand write.raw 0x10000 0x800 1 mw.b 0x1000020 0xff 1 nand write 0x1000000 0x800 0x1800 Example of a raw write which previously failed silently due to stuck data bit, but now errors out: nand erase 0 0x10000 dhcp /somefile mw.b 0x10000 0xff 0x2000 mw.b 0x10020 0xfe 1 nand write.raw 0x10000 0x800 1 mw.b 0x1000020 0x01 1 nand write.raw 0x1000000 0x800 3 Example of a raw write which previously failed silently due to stuck OOB bit, but now errors out: nand erase 0 0x10000 dhcp /somefile mw.b 0x10000 0xff 0x2000 mw.b 0x10810 0xfe 1 nand write.raw 0x10000 0x800 1 mw.b 0x1000810 0x01 1 nand write.raw 0x1000000 0x800 3 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | nand: Add verification functionsPeter Tyser2015-03-30-1/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies NAND contents against an arbitrarily sized buffer using ECC while nand_verify_page_oob() verifies a NAND page's contents and OOB. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | nand: Remove unused read/write structuresPeter Tyser2015-03-30-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of the nand_write_options and nand_read_options structures were removed in commit dfbf617ff055e4216f78d358b0867c548916d14b. Remove the now-unused structures too. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | | nand: Remove unused CONFIG_MTD_NAND_ECC_JFFS2 optionPeter Tyser2015-03-30-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This option was removed along with legacy NAND support in be33b046b549ad88c204c209508cd7657232ffbd. Clean up some remnants. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_write_buf()Luca Ellero2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
| * | | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_read_buf()Luca Ellero2015-03-30-1/+1
| |/ / | | | | | | | | | | | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2015-03-31-2/+803
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| * | | watchdog/imx_watchdog: do not set WCR_WDWSebastian Siewior2015-03-25-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with WCR_WDW set, the watchdog won't trigger if we bootet linux and idle around while the watchdog is not triggered. It seems the timer makes progress very slowly if at all. I managed to remain 20minutes alive while the timeout was set to 60secs. It reboots within 60secs if I start a busyloop in userland (something like "while (1) { }"). While I don't see a reason why the WDT should not be running while the CPU is in idle, I'm dropping this bit. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | imx:mx6slevk support reading temperaturePeng Fan2015-03-23-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to support reading temperature for mx6slevk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx:mx6dlsabresd fix error detecting thermalPeng Fan2015-03-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before add CONFIG_SYS_MALLOC_F and CONFIG_SYS_MALLOC_F_LEN, uboot will complains "CPU: Temperature: Can't find sensor device". This is because DM and DM_THERMAL are enabled, but SYS_MALLOC_F is not configured. After applying this patch, uboot can correctly detect the temperature. " U-Boot 2015.04-rc2-00146-g48b6e30-dirty (Mar 09 2015 - 13:04:36) CPU: Freescale i.MX6DL rev1.1 at 792 MHz CPU: Temperature 44 C " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | board/seco: Add mx6q-uq7 basic board supportBoris BREZILLON2015-03-23-0/+744
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | | ARM: iMX: define an IMX_CONFIG Kconfig optionBoris BREZILLON2015-03-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked as deprecated. Add a new Kconfig file under arch/arm/imx-common and define the IMX_CONFIG Kconfig in there. Each board is supposed to provide a default value pointing to the appropriate imximage.cfg file. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | | ARM: mx6: move to a standard arch/board approachBoris BREZILLON2015-03-23-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale boards are currently all defined in arch/arm/Kconfig, which makes them hard to detect. Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently done via the SYS_EXTRA_OPTIONS option which marked as deprecated. Move to a more standard way to select sub-architecture and board by creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6 option. Existing MX6 board definitions should be moved in this new Kconfig in choice menu, and new boards should be directly declared in this menu. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* | | | spi: designware_spi: revisit FIFO size detection againAxel Lin2015-03-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-12-19 20:29:54 +0000